diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-01-13 09:21:32 +0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2012-02-18 14:55:51 +0400 |
| commit | e61dc8f72c096e084106d5e97101d9d88f642d0e (patch) | |
| tree | 9f1040d377372c4771d9f061bd163fac5ea7e41b /target-xtensa/helper.c | |
| parent | ab58c5b4fd07fbe94950ff459ef51d43cfb5b8c8 (diff) | |
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and
BREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.
On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa/helper.c')
| -rw-r--r-- | target-xtensa/helper.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 973c268db5..0a26f8dd3a 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -44,6 +44,7 @@ void cpu_reset(CPUXtensaState *env) env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; + env->sregs[IBREAKENABLE] = 0; env->pending_irq_level = 0; reset_mmu(env); @@ -193,6 +194,7 @@ void do_interrupt(CPUState *env) case EXC_KERNEL: case EXC_USER: case EXC_DOUBLE: + case EXC_DEBUG: qemu_log_mask(CPU_LOG_INT, "%s(%d) " "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", __func__, env->exception_index, |