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authorAndreas Färber <afaerber@suse.de>2013-07-07 01:47:51 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-26 23:23:17 +0200
commit67cce5617ee968946fc6402f02743fffaa4a1a02 (patch)
tree9cf4bedac9ecbda2e4fa40a5cf5d11dd478e99b2 /target-xtensa/cpu-qom.h
parent9282b73a4078f10b5d1c96707aeed213eedbc8e1 (diff)
target-xtensa: Introduce XtensaCPU subclasses
Register a CPU type per core registered. Save the XtensaConfig in XtensaCPUClass and copy it from there to CPUXtensaState, to avoid touching every env->config access for now. Prepares for storing per-class GDB register count. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-xtensa/cpu-qom.h')
-rw-r--r--target-xtensa/cpu-qom.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index b9896f2647..1b9479eb9c 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -45,6 +45,7 @@
* XtensaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
+ * @config: The CPU core configuration.
*
* An Xtensa CPU model.
*/
@@ -55,6 +56,8 @@ typedef struct XtensaCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+
+ const XtensaConfig *config;
} XtensaCPUClass;
/**