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author | Max Filippov <jcmvbkbc@gmail.com> | 2014-02-15 20:58:47 +0400 |
---|---|---|
committer | Max Filippov <jcmvbkbc@gmail.com> | 2014-02-24 04:47:02 +0400 |
commit | 676056d4f1598f3f368da26fdc43371e8ab3a7fb (patch) | |
tree | 690db82e98183da5baf56ddb814e2faf775bbd28 /target-xtensa/core-dc232b.c | |
parent | 2c09eee112677c64a5e060eb9d491981843d7531 (diff) |
target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa/core-dc232b.c')
-rw-r--r-- | target-xtensa/core-dc232b.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c index 0bfcf2414c..c51e11e6d7 100644 --- a/target-xtensa/core-dc232b.c +++ b/target-xtensa/core-dc232b.c @@ -35,7 +35,6 @@ static const XtensaConfig dc232b = { .name = "dc232b", - .options = XTENSA_OPTIONS, .gdb_regmap = { .num_regs = 120, .num_core_regs = 52, @@ -43,13 +42,8 @@ static const XtensaConfig dc232b = { #include "core-dc232b/gdb-config.c" } }, - .nareg = XCHAL_NUM_AREGS, - .ndepc = 1, - EXCEPTIONS_SECTION, - INTERRUPTS_SECTION, - TLB_SECTION, - DEBUG_SECTION, .clock_freq_khz = 10000, + DEFAULT_SECTIONS }; REGISTER_CORE(dc232b) |