diff options
| author | Richard Henderson <rth@twiddle.net> | 2012-10-16 19:32:18 +1000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-10-20 07:56:06 +0000 |
| commit | a4273524875a960e8ef22ed676853e5988fefbea (patch) | |
| tree | f1c687daf0490a00920a238cc69de030a7e0e6ec /target-sparc/translate.c | |
| parent | 81634eea3d5dada203848f89ebd97d6a05aa4cce (diff) | |
target-sparc: Cleanup cpu_src[12] allocation
Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.
Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 3c9b0e3412..2a95c1fdeb 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2483,7 +2483,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) static void disas_sparc_insn(DisasContext * dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2; + TCGv cpu_src1, cpu_src2; TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; @@ -2496,9 +2496,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) rd = GET_FIELD(insn, 2, 6); - cpu_tmp1 = cpu_src1 = tcg_temp_new(); - cpu_tmp2 = cpu_src2 = tcg_temp_new(); - switch (opc) { case 0: /* branches/sethi */ { @@ -4602,8 +4599,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); tcg_gen_mov_tl(cpu_addr, cpu_src1); } else if (IS_IMM) { /* immediate */ simm = GET_FIELDs(insn, 19, 31); @@ -5074,9 +5069,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; case 0x3c: /* V9 casa */ + rs2 = GET_FIELD(insn, 27, 31); + cpu_src2 = gen_load_gpr(dc, rs2); gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); break; case 0x3e: /* V9 casxa */ + rs2 = GET_FIELD(insn, 27, 31); + cpu_src2 = gen_load_gpr(dc, rs2); gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); break; #else @@ -5089,8 +5088,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) default: goto illegal_insn; } - } else + } else { goto illegal_insn; + } } break; } @@ -5169,8 +5169,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto egress; #endif egress: - tcg_temp_free(cpu_tmp1); - tcg_temp_free(cpu_tmp2); if (dc->n_t32 != 0) { int i; for (i = dc->n_t32 - 1; i >= 0; --i) { |