full system SPARC emulation (Blue Swirl)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1083 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 95 insertions, 3 deletions

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index e86fae9e7c..ec9bba76a6 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -9,8 +9,10 @@
 
 /* trap definitions */
 #define TT_ILL_INSN 0x02
+#define TT_PRIV_INSN 0x03
 #define TT_WIN_OVF  0x05
 #define TT_WIN_UNF  0x06 
+#define TT_FP_EXCP  0x08
 #define TT_DIV_ZERO 0x2a
 #define TT_TRAP     0x80
 
@@ -18,27 +20,101 @@
 #define PSR_ZERO  (1<<22)
 #define PSR_OVF   (1<<21)
 #define PSR_CARRY (1<<20)
+#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
+#define PSR_S     (1<<7)
+#define PSR_PS    (1<<6)
+#define PSR_ET    (1<<5)
+#define PSR_CWP   0x1f
+/* Fake impl 0, version 4 */
+#define GET_PSR(env) ((0<<28) | (4<<24) | env->psr | (env->psrs? PSR_S : 0) | (env->psrs? PSR_PS : 0) |(env->psret? PSR_ET : 0) | env->cwp)
+
+/* Trap base register */
+#define TBR_BASE_MASK 0xfffff000
+
+/* Fcc */
+#define FSR_RD1        (1<<31)
+#define FSR_RD0        (1<<30)
+#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
+#define FSR_RD_NEAREST 0
+#define FSR_RD_ZERO    FSR_RD0
+#define FSR_RD_POS     FSR_RD1
+#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
+
+#define FSR_NVM   (1<<27)
+#define FSR_OFM   (1<<26)
+#define FSR_UFM   (1<<25)
+#define FSR_DZM   (1<<24)
+#define FSR_NXM   (1<<23)
+#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
+
+#define FSR_NVA   (1<<9)
+#define FSR_OFA   (1<<8)
+#define FSR_UFA   (1<<7)
+#define FSR_DZA   (1<<6)
+#define FSR_NXA   (1<<5)
+#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+
+#define FSR_NVC   (1<<4)
+#define FSR_OFC   (1<<3)
+#define FSR_UFC   (1<<2)
+#define FSR_DZC   (1<<1)
+#define FSR_NXC   (1<<0)
+#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
+
+#define FSR_FTT2   (1<<16)
+#define FSR_FTT1   (1<<15)
+#define FSR_FTT0   (1<<14)
+#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+
+#define FSR_FCC1  (1<<11)
+#define FSR_FCC0  (1<<10)
+
+/* MMU */
+#define MMU_E	  (1<<0)
+#define MMU_NF	  (1<<1)
+
+#define PTE_ENTRYTYPE_MASK 3
+#define PTE_ACCESS_MASK    0x1c
+#define PTE_ACCESS_SHIFT   2
+#define PTE_ADDR_MASK      0xffffff00
+
+#define PG_ACCESSED_BIT	5
+#define PG_MODIFIED_BIT	6
+#define PG_CACHE_BIT    7
+
+#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
+#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
+#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
+
+#define ACCESS_DATA	0
+#define ACCESS_CODE	1
+#define ACCESS_MMU	2
 
 #define NWINDOWS  32
 
 typedef struct CPUSPARCState {
     uint32_t gregs[8]; /* general registers */
     uint32_t *regwptr; /* pointer to current register window */
-    double   *regfptr; /* floating point registers */
+    float    fpr[32];  /* floating point registers */
     uint32_t pc;       /* program counter */
     uint32_t npc;      /* next program counter */
-    uint32_t sp;       /* stack pointer */
     uint32_t y;        /* multiply/divide register */
     uint32_t psr;      /* processor state register */
+    uint32_t fsr;      /* FPU state register */
     uint32_t T2;
     uint32_t cwp;      /* index of current register window (extracted
                           from PSR) */
     uint32_t wim;      /* window invalid mask */
+    uint32_t tbr;      /* trap base register */
+    int      psrs;     /* supervisor mode (extracted from PSR) */
+    int      psrps;    /* previous supervisor mode */
+    int      psret;    /* enable traps */
     jmp_buf  jmp_env;
     int user_mode_only;
     int exception_index;
     int interrupt_index;
     int interrupt_request;
+    uint32_t exception_next_pc;
     struct TranslationBlock *current_tb;
     void *opaque;
     /* NOTE: we allow 8 more registers to handle wrapping */
@@ -51,6 +127,22 @@ typedef struct CPUSPARCState {
                                    written */
     unsigned long mem_write_vaddr; /* target virtual addr at which the
                                       memory was written */
+    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
+    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
+    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
+    int error_code;
+    int access_type;
+    /* MMU regs */
+    uint32_t mmuregs[16];
+    /* temporary float registers */
+    float ft0, ft1, ft2;
+    double dt0, dt1, dt2;
+
+    /* ice debug support */
+    uint32_t breakpoints[MAX_BREAKPOINTS];
+    int nb_breakpoints;
+    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
+
 } CPUSPARCState;
 
 CPUSPARCState *cpu_sparc_init(void);
@@ -61,7 +153,7 @@ struct siginfo;
 int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
 void cpu_sparc_dump_state(CPUSPARCState *env, FILE *f, int flags);
 
-#define TARGET_PAGE_BITS 13
+#define TARGET_PAGE_BITS 12 /* 4k */
 #include "cpu-all.h"
 
 #endif