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authorAurelien Jarno <aurelien@aurel32.net>2011-01-13 08:20:39 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-01-16 13:19:20 +0100
commit2411fde9a41323310d472dd352006989f30049b2 (patch)
tree045a1b430c9b6c637e2f68c2a8f932efb53e3dff /target-sh4
parent4cd31ad264b11274f199bbd8e96474d8cde60c42 (diff)
target-sh4: use rotl/rotr when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4')
-rw-r--r--target-sh4/translate.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c8fffbc4c3..743d76a575 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1690,14 +1690,12 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0x4004: /* rotl Rn */
- gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
- tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
- gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
+ tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1);
+ gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
return;
case 0x4005: /* rotr Rn */
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
- tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
- gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
+ tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1);
return;
case 0x4000: /* shll Rn */
case 0x4020: /* shal Rn */