diff options
author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-14 12:17:09 +0000 |
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committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-14 12:17:09 +0000 |
commit | e96efcfcb19b81d87ed3baec419b14cdd6e021a4 (patch) | |
tree | 8889bad1c84ecf82704c967f9e52351ac3a13822 /target-ppc | |
parent | ba13c4327e19c083dd76d69805c5bf3dd44ca46c (diff) |
Fix miscellaneous display warnings for PowerPC & alpha targets
and parallel CFI flash driver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r-- | target-ppc/cpu.h | 8 | ||||
-rw-r--r-- | target-ppc/helper.c | 10 |
2 files changed, 10 insertions, 8 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 4b67f1a25c..740bc1b4cf 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -35,24 +35,26 @@ typedef uint64_t ppc_gpr_t; #define TARGET_LONG_BITS 64 #define TARGET_GPR_BITS 64 #define REGX "%016" PRIx64 -#define ADDRX "%016" PRIx64 #elif defined(TARGET_PPCSPE) +/* e500v2 have 36 bits physical address space */ +#define TARGET_PHYS_ADDR_BITS 64 /* GPR are 64 bits: used by vector extension */ typedef uint64_t ppc_gpr_t; #define TARGET_LONG_BITS 32 #define TARGET_GPR_BITS 64 #define REGX "%016" PRIx64 -#define ADDRX "%08" PRIx32 #else typedef uint32_t ppc_gpr_t; #define TARGET_LONG_BITS 32 #define TARGET_GPR_BITS 32 #define REGX "%08" PRIx32 -#define ADDRX "%08" PRIx32 #endif #include "cpu-defs.h" +#define ADDRX TARGET_FMT_lx +#define PADDRX TARGET_FMT_plx + #include <setjmp.h> #include "softfloat.h" diff --git a/target-ppc/helper.c b/target-ppc/helper.c index b9a55b1f2b..a7d0391827 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -38,7 +38,7 @@ /* PowerPC MMU emulation */ #if defined(CONFIG_USER_ONLY) -int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, +int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu) { int exception, error_code; @@ -631,7 +631,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx, } int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx, - uint32_t address, int rw, int access_type) + target_ulong address, int rw, int access_type) { ppcemb_tlb_t *tlb; target_phys_addr_t raddr; @@ -649,8 +649,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx, } mask = ~(tlb->size - 1); if (loglevel) { - fprintf(logfile, "%s: TLB %d address %08x PID %04x <=> " - "%08x %08x %04x\n", + fprintf(logfile, "%s: TLB %d address " ADDRX " PID " ADDRX " <=> " + ADDRX " " ADDRX " " ADDRX "\n", __func__, i, address, env->spr[SPR_40x_PID], tlb->EPN, mask, tlb->PID); } @@ -832,7 +832,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) } /* Perform address translation */ -int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, +int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu) { mmu_ctx_t ctx; |