diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-10 15:02:24 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-10 15:02:24 +0000 |
| commit | fe463b7dbc16cc66f3b9a8b7be197fb340378fa3 (patch) | |
| tree | 0ea6e365ecbd649ebbebe695ab80598b54750314 /target-ppc | |
| parent | 32938e127f50a40844a0fb9c5abb8691aeeccf7e (diff) | |
target-ppc: initialize MSR appropriately in user-mode
Mask the initial MSR with the mask from the PowerPC CPU definition.
Noticed by Nathan Froyd.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c index e22f6dd180..689291ccb2 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2904,12 +2904,12 @@ void cpu_ppc_reset (void *opaque) #if defined(CONFIG_USER_ONLY) msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ msr |= (target_ulong)1 << MSR_PR; + env->msr = msr & env->msr_mask; #else env->nip = env->hreset_vector | env->excp_prefix; if (env->mmu_model != POWERPC_MMU_REAL) ppc_tlb_invalidate_all(env); #endif - env->msr = msr; hreg_compute_hflags(env); env->reserve = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ |