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authorj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-14 09:14:08 +0000
committerj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-14 09:14:08 +0000
commita13d7523cb4205e633e947d37559ef3a281c323e (patch)
treeedd66152de1d85bb7934b79cb62f1744bf146f93 /target-ppc
parenteacc324914c2dc7aecec3b4ea920252b685b5c8e (diff)
There is no need of a specific MMU model for PowerPC 601.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h2
-rw-r--r--target-ppc/helper.c21
-rw-r--r--target-ppc/translate_init.c5
3 files changed, 1 insertions, 27 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index d39bd971a0..c6fc16ecbf 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -88,8 +88,6 @@ enum {
POWERPC_MMU_UNKNOWN = 0,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B,
- /* PowerPC 601 MMU */
- POWERPC_MMU_601,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx,
/* PowerPC 74xx MMU with software TLB */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index eeba478bee..12c8e71afa 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1280,7 +1280,6 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
case POWERPC_MMU_32B:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
- case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_REAL_4xx:
case POWERPC_MMU_BOOKE:
@@ -1365,10 +1364,6 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
ret = mmu40x_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "601 MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type);
@@ -1462,10 +1457,6 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
env->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
@@ -1562,10 +1553,6 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
else
env->spr[SPR_DSISR] = 0x40000000;
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
@@ -1796,10 +1783,6 @@ void ppc_tlb_invalidate_all (CPUPPCState *env)
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- break;
case POWERPC_MMU_32B:
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
@@ -1839,10 +1822,6 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- break;
case POWERPC_MMU_32B:
/* tlbie invalidate TLBs for all segments */
addr &= ~((target_ulong)-1 << 28);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0210de8538..41a4c64100 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3196,7 +3196,7 @@ static void init_proc_e500 (CPUPPCState *env)
#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
-//#define POWERPC_MMU_601 (POWERPC_MMU_601)
+#define POWERPC_MMU_601 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
@@ -6232,9 +6232,6 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
case POWERPC_MMU_32B:
mmu_model = "PowerPC 32";
break;
- case POWERPC_MMU_601:
- mmu_model = "PowerPC 601";
- break;
case POWERPC_MMU_SOFT_6xx:
mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
break;