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| author | Tom Musta <tommusta@gmail.com> | 2014-11-12 15:46:01 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:25 +0100 |
| commit | 14ba79c73a1c2db78becef171ec2f73606c1d7e1 (patch) | |
| tree | 8d61531b379d053f9f9c462e68d0f02abe5b52e3 /target-ppc | |
| parent | 4814f2d116c057d6fdfd57f3b979c77d5668e878 (diff) | |
target-ppc: mffs. Should Set CR1 from FPSCR Bits
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 35c3a16091..32c9f49fe0 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2504,7 +2504,9 @@ static void gen_mffs(DisasContext *ctx) } gen_reset_fpstatus(); tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* mtfsb0 */ |