diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-26 23:54:22 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-26 23:54:22 +0000 |
| commit | a750fc0b9184a520d00d9e949160a0c6d3232ecd (patch) | |
| tree | 681734fa2531d1cb27efc89d2f4d7397f1f8eaee /target-ppc/translate_init.c | |
| parent | 08fa4bab833f834e1511853dd2331fa3d6d5d469 (diff) | |
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate_init.c')
| -rw-r--r-- | target-ppc/translate_init.c | 5430 |
1 files changed, 3290 insertions, 2140 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 82270e659e..c6f09aea5a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -32,20 +32,26 @@ struct ppc_def_t { uint32_t pvr; uint32_t pvr_mask; uint64_t insns_flags; - uint32_t flags; uint64_t msr_mask; + uint8_t mmu_model; + uint8_t excp_model; + uint8_t bus_model; + uint8_t pad; + void (*init_proc)(CPUPPCState *env); }; /* For user-mode emulation, we don't emulate any IRQ controller */ #if defined(CONFIG_USER_ONLY) -#define PPC_IRQ_INIT_FN(name) \ -static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ -{ \ +#define PPC_IRQ_INIT_FN(name) \ +static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ +{ \ } #else -#define PPC_IRQ_INIT_FN(name) \ +#define PPC_IRQ_INIT_FN(name) \ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env); #endif + +PPC_IRQ_INIT_FN(401); PPC_IRQ_INIT_FN(405); PPC_IRQ_INIT_FN(6xx); PPC_IRQ_INIT_FN(970); @@ -285,7 +291,7 @@ static void spr_write_asr (void *opaque, int sprn) RET_STOP(ctx); } #endif -#endif /* !defined(CONFIG_USER_ONLY) */ +#endif /* PowerPC 601 specific registers */ /* RTC */ @@ -582,7 +588,7 @@ static void gen_low_BATs (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_dbat, &spr_write_dbatl, 0x00000000); - env->nb_BATs = 4; + env->nb_BATs += 4; } /* BATs 4-7 */ @@ -652,7 +658,7 @@ static void gen_high_BATs (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_dbat_h, &spr_write_dbatl_h, 0x00000000); - env->nb_BATs = 8; + env->nb_BATs += 4; } /* Generic PowerPC time base */ @@ -797,7 +803,7 @@ static void gen_spr_7xx (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_SIA, "SIA", + spr_register(env, SPR_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); @@ -825,29 +831,33 @@ static void gen_spr_7xx (CPUPPCState *env) &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); - spr_register(env, SPR_USIA, "USIA", + spr_register(env, SPR_USIAR, "USIAR", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); - /* Thermal management */ + /* External access control */ /* XXX : not implemented */ - spr_register(env, SPR_THRM1, "THRM1", + spr_register(env, SPR_EAR, "EAR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); +} + +static void gen_spr_thrm (CPUPPCState *env) +{ + /* Thermal management */ /* XXX : not implemented */ - spr_register(env, SPR_THRM2, "THRM2", + spr_register(env, SPR_THRM1, "THRM1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_THRM3, "THRM3", + spr_register(env, SPR_THRM2, "THRM2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - /* External access control */ /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", + spr_register(env, SPR_THRM3, "THRM3", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -904,7 +914,7 @@ static void gen_spr_604 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_SIA, "SIA", + spr_register(env, SPR_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); @@ -1004,7 +1014,7 @@ static void gen_spr_602 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_ESASR, "ESASR", + spr_register(env, SPR_ESASRR, "ESASRR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -1030,6 +1040,11 @@ static void gen_spr_602 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); } /* SPR specific to PowerPC 601 implementation */ @@ -1104,8 +1119,117 @@ static void gen_spr_601 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_601_ubat, &spr_write_601_ubatl, 0x00000000); + env->nb_BATs = 4; } +static void gen_spr_74xx (CPUPPCState *env) +{ + /* Processor identification */ + spr_register(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MMCR2, "MMCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UMMCR2, "UMMCR2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX: not implemented */ + spr_register(env, SPR_BAMR, "BAMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_MSSCR0, "MSSCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Altivec */ + spr_register(env, SPR_VRSAVE, "VRSAVE", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +#if defined (TODO) +static void gen_l3_ctrl (CPUPPCState *env) +{ + /* L3CR */ + /* XXX : not implemented */ + spr_register(env, SPR_L3CR, "L3CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR0 */ + spr_register(env, SPR_L3ITCR0, "L3ITCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR1 */ + spr_register(env, SPR_L3ITCR1, "L3ITCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR2 */ + spr_register(env, SPR_L3ITCR2, "L3ITCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR3 */ + spr_register(env, SPR_L3ITCR3, "L3ITCR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3OHCR */ + spr_register(env, SPR_L3OHCR, "L3OHCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3PM */ + spr_register(env, SPR_L3PM, "L3PM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} +#endif /* TODO */ + +#if defined (TODO) +static void gen_74xx_soft_tlb (CPUPPCState *env) +{ + /* XXX: TODO */ + spr_register(env, SPR_PTEHI, "PTEHI", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_PTELO, "PTELO", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_TLBMISS, "TLBMISS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} +#endif /* TODO */ + /* PowerPC BookE SPR */ static void gen_spr_BookE (CPUPPCState *env) { @@ -1132,14 +1256,6 @@ static void gen_spr_BookE (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); #endif /* Debug */ /* XXX : not implemented */ @@ -1366,6 +1482,7 @@ static void gen_spr_BookE (CPUPPCState *env) } /* FSL storage control registers */ +#if defined(TODO) static void gen_spr_BookE_FSL (CPUPPCState *env) { /* TLB assist registers */ @@ -1447,6 +1564,7 @@ static void gen_spr_BookE_FSL (CPUPPCState *env) break; } } +#endif /* SPR specific to PowerPC 440 implementation */ static void gen_spr_440 (CPUPPCState *env) @@ -1599,11 +1717,6 @@ static void gen_spr_40x (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ spr_register(env, SPR_40x_ICCR, "ICCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -1613,11 +1726,6 @@ static void gen_spr_40x (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); - /* Bus access control */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); /* Exception */ spr_register(env, SPR_40x_DEAR, "DEAR", SPR_NOACCESS, SPR_NOACCESS, @@ -1834,6 +1942,19 @@ static void gen_spr_401 (CPUPPCState *env) 0x00000000); } +static void gen_spr_401x2 (CPUPPCState *env) +{ + gen_spr_401(env); + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_ZPR, "ZPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + /* SPR specific to PowerPC 403 implementation */ static void gen_spr_403 (CPUPPCState *env) { @@ -1867,11 +1988,10 @@ static void gen_spr_403 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); +} + +static void gen_spr_403_real (CPUPPCState *env) +{ spr_register(env, SPR_403_PBL1, "PBL1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_403_pbr, &spr_write_403_pbr, @@ -1888,6 +2008,15 @@ static void gen_spr_403 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_403_pbr, &spr_write_403_pbr, 0x00000000); +} + +static void gen_spr_403_mmu (CPUPPCState *env) +{ + /* MMU */ + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); spr_register(env, SPR_40x_ZPR, "ZPR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -1895,7 +2024,6 @@ static void gen_spr_403 (CPUPPCState *env) } /* SPR specific to PowerPC compression coprocessor extension */ -#if defined (TODO) static void gen_spr_compress (CPUPPCState *env) { spr_register(env, SPR_401_SKR, "SKR", @@ -1903,14 +2031,93 @@ static void gen_spr_compress (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); } + +#if defined (TARGET_PPC64) +#if defined (TODO) +/* SPR specific to PowerPC 620 */ +static void gen_spr_620 (CPUPPCState *env) +{ + spr_register(env, SPR_620_PMR0, "PMR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR1, "PMR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR2, "PMR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR3, "PMR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR4, "PMR4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR5, "PMR5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR6, "PMR6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR7, "PMR7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR8, "PMR8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMR9, "PMR9", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRA, "PMR10", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRB, "PMR11", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRC, "PMR12", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRD, "PMR13", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRE, "PMR14", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_PMRF, "PMR15", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_HID8, "HID8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_620_HID9, "HID9", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} #endif +#endif /* defined (TARGET_PPC64) */ // XXX: TODO /* * AMR => SPR 29 (Power 2.04) * CTRL => SPR 136 (Power 2.04) * CTRL => SPR 152 (Power 2.04) - * VRSAVE => SPR 256 (Altivec) * SCOMC => SPR 276 (64 bits ?) * SCOMD => SPR 277 (64 bits ?) * ASR => SPR 280 (64 bits) @@ -1942,573 +2149,2901 @@ static void gen_spr_compress (CPUPPCState *env) * ... and more (thermal management, performance counters, ...) */ -static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) +/*****************************************************************************/ +/* PowerPC implementations definitions */ + +/* PowerPC 40x instruction set */ +#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON) + +/* PowerPC 401 */ +#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_401 (0x00000000000FD201ULL) +#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx) +#define POWERPC_EXCP_401 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401) + +static void init_proc_401 (CPUPPCState *env) { - env->reserve = -1; - /* Default MMU definitions */ - env->nb_BATs = -1; - env->nb_tlb = 0; - env->nb_ways = 0; - /* XXX: missing: - * 32 bits PowerPC: - * - MPC5xx(x) - * - MPC8xx(x) - * - RCPU (same as MPC5xx ?) - */ - spr_register(env, SPR_PVR, "PVR", + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401(env); + /* Bus access control */ + spr_register(env, SPR_40x_SGR, "SGR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - def->pvr); - printf("%s: PVR %08x mask %08x => %08x\n", __func__, - def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); - switch (def->pvr) { - /* Embedded PowerPC from IBM */ - case CPU_PPC_401A1: /* 401 A1 family */ - case CPU_PPC_401B2: /* 401 B2 family */ -#if 0 - case CPU_PPC_401B3: /* 401 B3 family */ -#endif - case CPU_PPC_401C2: /* 401 C2 family */ - case CPU_PPC_401D2: /* 401 D2 family */ - case CPU_PPC_401E2: /* 401 E2 family */ - case CPU_PPC_401F2: /* 401 F2 family */ - case CPU_PPC_401G2: /* 401 G2 family */ - case CPU_PPC_IOP480: /* IOP 480 family */ - case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ - gen_spr_generic(env); - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_401(env); + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 401x2 */ +#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_CACHE_DCBA | PPC_MFTB | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) +#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z) +#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401) + +static void init_proc_401x2 (CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401x2(env); + gen_spr_compress(env); + /* Bus access control */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 401x3 */ +#if defined(TODO) +#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_CACHE_DCBA | PPC_MFTB | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) +#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z) +#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401) + +static void init_proc_401x2 (CPUPPCState *env) +{ +} +#endif /* TODO */ + +/* IOP480 */ +#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_CACHE_DCBA | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) +#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z) +#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401) + +static void init_proc_IOP480 (CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401x2(env); + gen_spr_compress(env); + /* Bus access control */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 403 */ +#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_403 (0x000000000007D00DULL) +#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx) +#define POWERPC_EXCP_403 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401) + +static void init_proc_403 (CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_403(env); + gen_spr_403_real(env); + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 403 GCX */ +#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define POWERPC_MSRM_403GCX (0x000000000007D00DULL) +#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z) +#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x) +#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401) + +static void init_proc_403GCX (CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_403(env); + gen_spr_403_real(env); + gen_spr_403_mmu(env); + /* Bus access control */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 405 */ +#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \ + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \ + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \ + PPC_405_MAC) +#define POWERPC_MSRM_405 (0x000000000006E630ULL) +#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx) +#define POWERPC_EXCP_405 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405) + +static void init_proc_405 (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_40x(env); + gen_spr_405(env); + /* Bus access control */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* Allocate hardware IRQ controller */ + ppc405_irq_init(env); +} + +/* PowerPC 440 EP */ +#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ + PPC_440_SPEC | PPC_RFMCI) +#define POWERPC_MSRM_440EP (0x000000000006D630ULL) +#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE) + +static void init_proc_440EP (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + gen_spr_440(env); + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_440_CCR1, "CCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 440 GP */ +#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \ + PPC_405_MAC | PPC_440_SPEC) +#define POWERPC_MSRM_440GP (0x000000000006FF30ULL) +#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE) + +static void init_proc_440GP (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + gen_spr_440(env); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 440x4 */ +#if defined(TODO) +#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ + PPC_440_SPEC) +#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL) +#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE) + +static void init_proc_440x4 (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + gen_spr_440(env); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} +#endif /* TODO */ + +/* PowerPC 440x5 */ +#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ + PPC_440_SPEC | PPC_RFMCI) +#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL) +#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE) + +static void init_proc_440x5 (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + gen_spr_440(env); + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_440_CCR1, "CCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 460 (guessed) */ +#if defined(TODO) +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \ + PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX) +#define POWERPC_MSRM_460 (0x000000000006FF30ULL) +#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE) + +static void init_proc_460 (CPUPPCState *env) +{ +} +#endif /* TODO */ + +/* PowerPC 460F (guessed) */ +#if defined(TODO) +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \ + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ + PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \ + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ + PPC_FLOAT_STFIWX | \ + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \ + PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX) +#define POWERPC_MSRM_460 (0x000000000006FF30ULL) +#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE) + +static void init_proc_460 (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + gen_spr_440(env); + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_440_CCR1, "CCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} +#endif /* TODO */ + +/* Generic BookE PowerPC */ +#if defined(TODO) +#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \ + PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \ + PPC_CACHE_DCBA | \ + PPC_FLOAT | PPC_FLOAT_FSQRT | \ + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \ + PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \ + PPC_BOOKE) +#define POWERPC_MSRM_BookE (0x000000000006D630ULL) +#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE) +#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE) + +static void init_proc_BookE (CPUPPCState *env) +{ +} +#endif /* TODO */ + +/* e200 core */ +#if defined(TODO) +#endif /* TODO */ + +/* e300 core */ +#if defined(TODO) +#endif /* TODO */ + +/* e500 core */ +#if defined(TODO) +#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \ + PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \ + PPC_CACHE_DCBA | \ + PPC_BOOKE | PPC_E500_VECTOR) +#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx) +#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x) +#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE) + +static void init_proc_e500 (CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env); + /* Memory management */ + gen_spr_BookE_FSL(env); + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} +#endif /* TODO */ + +/* e600 core */ +#if defined(TODO) +#endif /* TODO */ + +/* Non-embedded PowerPC */ +/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */ +#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \ + PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE) +/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */ +#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \ + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \ + PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \ + PPC_MEM_TLBSYNC | PPC_MFTB) + +/* POWER : same as 601, without mfmsr, mfsr */ +#if defined(TODO) +#define POWERPC_INSNS_POWER (XXX_TODO) +/* POWER RSC (from RAD6000) */ +#define POWERPC_MSRM_POWER (0x00000000FEF0ULL) +#endif /* TODO */ + +/* PowerPC 601 */ +#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR) +#define POWERPC_MSRM_601 (0x000000000000FE70ULL) +//#define POWERPC_MMU_601 (POWERPC_MMU_601) +//#define POWERPC_EXCP_601 (POWERPC_EXCP_601) +#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_601 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_601(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID5, "HID5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID15, "HID15", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + env->nb_tlb = 64; + env->nb_ways = 2; + env->id_tlbs = 0; + env->id_tlbs = 0; + /* XXX: TODO: allocate internal IRQ controller */ +} + +/* PowerPC 602 */ +#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \ + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \ + PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \ + PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC) +#define POWERPC_MSRM_602 (0x000000000033FF73ULL) +#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx) +//#define POWERPC_EXCP_602 (POWERPC_EXCP_602) +#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_602 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_602(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 603 */ +#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) +#define POWERPC_MSRM_603 (0x000000000001FF73ULL) +#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx) +//#define POWERPC_EXCP_603 (POWERPC_EXCP_603) +#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_603 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_603(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 603e */ +#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) +#define POWERPC_MSRM_603E (0x000000000007FF73ULL) +#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx) +//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E) +#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx) + +static void init_proc_603E (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_603(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC G2 */ +#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) +#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL) +#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx) +//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2) +#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_G2 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_G2_755(env); + gen_spr_G2(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation register */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC G2LE */ +#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) +#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL) +#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx) +#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2) +#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx) + +static void init_proc_G2LE (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_G2_755(env); + gen_spr_G2(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation register */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 604 */ +#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN) +#define POWERPC_MSRM_604 (0x000000000005FF77ULL) +#define POWERPC_MMU_604 (POWERPC_MMU_32B) +//#define POWERPC_EXCP_604 (POWERPC_EXCP_604) +#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_604 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_604(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 740/750 (aka G3) */ +#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN) +#define POWERPC_MSRM_7x0 (0x000000000007FF77ULL) +#define POWERPC_MMU_7x0 (POWERPC_MMU_32B) +//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0) +#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7x0 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 750FX/GX */ +#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN) +#define POWERPC_MSRM_750fx (0x000000000007FF77ULL) +#define POWERPC_MMU_750fx (POWERPC_MMU_32B) +#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0) +#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx) + +static void init_proc_750fx (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ + gen_high_BATs(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 745/755 */ +#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB) +#define POWERPC_MSRM_7x5 (0x000000000007FF77ULL) +#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx) +//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5) +#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7x5 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_G2_755(env); + /* Time base */ + gen_tbl(env); + /* L2 cache control */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTC, "ICTC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_L2PMCR, "L2PMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 7400 (aka G4) */ +#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7400 (0x000000000205FF77ULL) +#define POWERPC_MMU_7400 (POWERPC_MMU_32B) +#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7400 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Memory management */ + gen_low_BATs(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 7410 (aka G4) */ +#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7410 (0x000000000205FF77ULL) +#define POWERPC_MMU_7410 (POWERPC_MMU_32B) +#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7410 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Thermal management */ + gen_spr_thrm(env); + /* L2PMCR */ + /* XXX : not implemented */ + spr_register(env, SPR_L2PMCR, "L2PMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* LDSTDB */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTDB, "LDSTDB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +/* PowerPC 7440 (aka G4) */ #if defined (TODO) - /* XXX: optional ? */ - gen_spr_compress(env); -#endif - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* XXX: TODO: allocate internal IRQ controller */ - break; +#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7440 (0x000000000205FF77ULL) +#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx) +#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7440 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_74xx_soft_tlb(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} +#endif /* TODO */ - case CPU_PPC_403GA: /* 403 GA family */ - case CPU_PPC_403GB: /* 403 GB family */ - case CPU_PPC_403GC: /* 403 GC family */ - case CPU_PPC_403GCX: /* 403 GCX family */ - gen_spr_generic(env); - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_403(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* XXX: TODO: allocate internal IRQ controller */ - break; +/* PowerPC 7450 (aka G4) */ +#if defined (TODO) +#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7450 (0x000000000205FF77ULL) +#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx) +#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7450 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Level 3 cache control */ + gen_l3_ctrl(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_74xx_soft_tlb(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} +#endif /* TODO */ - case CPU_PPC_405CR: /* 405 GP/CR family */ - case CPU_PPC_405EP: /* 405 EP family */ - case CPU_PPC_405GPR: /* 405 GPR family */ - case CPU_PPC_405D2: /* 405 D2 family */ - case CPU_PPC_405D4: /* 405 D4 family */ - gen_spr_generic(env); - /* Time base */ - gen_tbl(env); - gen_spr_40x(env); - gen_spr_405(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* Allocate hardware IRQ controller */ - ppc405_irq_init(env); - break; +/* PowerPC 7445 (aka G4) */ +#if defined (TODO) +#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7445 (0x000000000205FF77ULL) +#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx) +#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7445 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} +#endif /* TODO */ - case CPU_PPC_NPE405H: /* NPe405 H family */ - case CPU_PPC_NPE405H2: - case CPU_PPC_NPE405L: /* Npe405 L family */ - gen_spr_generic(env); - /* Time base */ - gen_tbl(env); - gen_spr_40x(env); - gen_spr_405(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* Allocate hardware IRQ controller */ - ppc405_irq_init(env); - break; +/* PowerPC 7455 (aka G4) */ +#if defined (TODO) +#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \ + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ + PPC_ALTIVEC) +#define POWERPC_MSRM_7455 (0x000000000205FF77ULL) +#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx) +#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx) +#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx) + +static void init_proc_7455 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Level 3 cache control */ + gen_l3_ctrl(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env); + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} +#endif /* TODO */ +#if defined (TARGET_PPC64) +/* PowerPC 970 */ #if defined (TODO) - case CPU_PPC_STB01000: +#define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \ + PPC_64B | PPC_ALTIVEC | \ + PPC_64_BRIDGE | PPC_SLBI) +#define POWERPC_MSRM_970 (0x900000000204FF36ULL) +#define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE) +//#define POWERPC_EXCP_970 (POWERPC_EXCP_970) +#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970) + +static void init_proc_970 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + /* XXX: not correct */ + gen_low_BATs(env); +#if 0 // TODO + env->slb_nr = 32; #endif + /* Allocate hardware IRQ controller */ + ppc970_irq_init(env); +} +#endif /* TODO */ + +/* PowerPC 970FX (aka G5) */ #if defined (TODO) - case CPU_PPC_STB01010: +#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \ + PPC_64B | PPC_ALTIVEC | \ + PPC_64_BRIDGE | PPC_SLBI) +#define POWERPC_MSRM_970FX (0x800000000204FF36ULL) +#define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE) +#define POWERPC_EXCP_970FX (POWERPC_EXCP_970) +#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970) + +static void init_proc_970FX (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + /* XXX: not correct */ + gen_low_BATs(env); +#if 0 // TODO + env->slb_nr = 32; #endif + /* Allocate hardware IRQ controller */ + ppc970_irq_init(env); +} +#endif /* TODO */ + +/* PowerPC 970 GX */ #if defined (TODO) - case CPU_PPC_STB0210: +#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \ + PPC_64B | PPC_ALTIVEC | \ + PPC_64_BRIDGE | PPC_SLBI) +#define POWERPC_MSRM_970GX (0x800000000204FF36ULL) +#define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE) +#define POWERPC_EXCP_970GX (POWERPC_EXCP_970) +#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970) + +static void init_proc_970GX (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + /* XXX: not correct */ + gen_low_BATs(env); +#if 0 // TODO + env->slb_nr = 32; #endif - case CPU_PPC_STB03: /* STB03 family */ + /* Allocate hardware IRQ controller */ + ppc970_irq_init(env); +} +#endif /* TODO */ + +/* PowerPC 620 */ #if defined (TODO) - case CPU_PPC_STB043: /* STB043 family */ +#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \ + PPC_64B | PPC_SLBI) +#define POWERPC_MSRM_620 (0x800000000005FF73ULL) +#define POWERPC_MMU_620 (POWERPC_MMU_64B) +#define POWERPC_EXCP_620 (POWERPC_EXCP_970) +#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970) + +static void init_proc_620 (CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_620(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + /* XXX: TODO: initialize internal interrupt controller */ +} +#endif /* TODO */ +#endif /* defined (TARGET_PPC64) */ + +/* Default 32 bits PowerPC target will be 604 */ +#define CPU_POWERPC_PPC32 CPU_POWERPC_604 +#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604 +#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604 +#define POWERPC_MMU_PPC32 POWERPC_MMU_604 +#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604 +#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604 +#define init_proc_PPC32 init_proc_604 + +/* Default 64 bits PowerPC target will be 970 FX */ +#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX +#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX +#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX +#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX +#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX +#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX +#define init_proc_PPC64 init_proc_970FX + +/* Default PowerPC target will be PowerPC 32 */ +#if defined (TARGET_PPC64) && 0 // XXX: TODO +#define CPU_POWERPC_PPC CPU_POWERPC_PPC64 +#define POWERPC_INSNS_PPC POWERPC_INSNS_PPC64 +#define POWERPC_MSRM_PPC POWERPC_MSRM_PPC64 +#define POWERPC_MMU_PPC POWERPC_MMU_PPC64 +#define POWERPC_EXCP_PPC POWERPC_EXCP_PPC64 +#define POWERPC_INPUT_PPC POWERPC_INPUT_PPC64 +#define init_proc_PPC init_proc_PPC64 +#else +#define CPU_POWERPC_PPC CPU_POWERPC_PPC32 +#define POWERPC_INSNS_PPC POWERPC_INSNS_PPC32 +#define POWERPC_MSRM_PPC POWERPC_MSRM_PPC32 +#define POWERPC_MMU_PPC POWERPC_MMU_PPC32 +#define POWERPC_EXCP_PPC POWERPC_EXCP_PPC32 +#define POWERPC_INPUT_PPC POWERPC_INPUT_PPC32 +#define init_proc_PPC init_proc_PPC32 #endif -#if defined (TODO) - case CPU_PPC_STB045: /* STB045 family */ + +/*****************************************************************************/ +/* PVR definitions for most known PowerPC */ +enum { + /* PowerPC 401 family */ + /* Generic PowerPC 401 */ +#define CPU_POWERPC_401 CPU_POWERPC_401G2 + /* PowerPC 401 cores */ + CPU_POWERPC_401A1 = 0x00210000, + CPU_POWERPC_401B2 = 0x00220000, +#if 0 + CPU_POWERPC_401B3 = xxx, #endif - case CPU_PPC_STB25: /* STB25 family */ -#if defined (TODO) - case CPU_PPC_STB130: /* STB130 family */ -#endif - gen_spr_generic(env); - /* Time base */ - gen_tbl(env); - gen_spr_40x(env); - gen_spr_405(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* Allocate hardware IRQ controller */ - ppc405_irq_init(env); - break; + CPU_POWERPC_401C2 = 0x00230000, + CPU_POWERPC_401D2 = 0x00240000, + CPU_POWERPC_401E2 = 0x00250000, + CPU_POWERPC_401F2 = 0x00260000, + CPU_POWERPC_401G2 = 0x00270000, + /* PowerPC 401 microcontrolers */ +#if 0 + CPU_POWERPC_401GF = xxx, +#endif +#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 + /* IBM Processor for Network Resources */ + CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */ +#if 0 + CPU_POWERPC_XIPCHIP = xxx, +#endif + /* PowerPC 403 family */ + /* Generic PowerPC 403 */ +#define CPU_POWERPC_403 CPU_POWERPC_403GC + /* PowerPC 403 microcontrollers */ + CPU_POWERPC_403GA = 0x00200011, + CPU_POWERPC_403GB = 0x00200100, + CPU_POWERPC_403GC = 0x00200200, + CPU_POWERPC_403GCX = 0x00201400, +#if 0 + CPU_POWERPC_403GP = xxx, +#endif + /* PowerPC 405 family */ + /* Generic PowerPC 405 */ +#define CPU_POWERPC_405 CPU_POWERPC_405D4 + /* PowerPC 405 cores */ +#if 0 + CPU_POWERPC_405A3 = xxx, +#endif +#if 0 + CPU_POWERPC_405A4 = xxx, +#endif +#if 0 + CPU_POWERPC_405B3 = xxx, +#endif +#if 0 + CPU_POWERPC_405B4 = xxx, +#endif +#if 0 + CPU_POWERPC_405C3 = xxx, +#endif +#if 0 + CPU_POWERPC_405C4 = xxx, +#endif + CPU_POWERPC_405D2 = 0x20010000, +#if 0 + CPU_POWERPC_405D3 = xxx, +#endif + CPU_POWERPC_405D4 = 0x41810000, +#if 0 + CPU_POWERPC_405D5 = xxx, +#endif +#if 0 + CPU_POWERPC_405E4 = xxx, +#endif +#if 0 + CPU_POWERPC_405F4 = xxx, +#endif +#if 0 + CPU_POWERPC_405F5 = xxx, +#endif +#if 0 + CPU_POWERPC_405F6 = xxx, +#endif + /* PowerPC 405 microcontrolers */ + /* XXX: missing 0x200108a0 */ +#define CPU_POWERPC_405CR CPU_POWERPC_405CRc + CPU_POWERPC_405CRa = 0x40110041, + CPU_POWERPC_405CRb = 0x401100C5, + CPU_POWERPC_405CRc = 0x40110145, + CPU_POWERPC_405EP = 0x51210950, +#if 0 + CPU_POWERPC_405EXr = xxx, +#endif + CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */ +#if 0 + CPU_POWERPC_405FX = xxx, +#endif +#define CPU_POWERPC_405GP CPU_POWERPC_405GPd + CPU_POWERPC_405GPa = 0x40110000, + CPU_POWERPC_405GPb = 0x40110040, + CPU_POWERPC_405GPc = 0x40110082, + CPU_POWERPC_405GPd = 0x401100C4, +#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc + CPU_POWERPC_405GPR = 0x50910951, +#if 0 + CPU_POWERPC_405H = xxx, +#endif +#if 0 + CPU_POWERPC_405L = xxx, +#endif + CPU_POWERPC_405LP = 0x41F10000, +#if 0 + CPU_POWERPC_405PM = xxx, +#endif +#if 0 + CPU_POWERPC_405PS = xxx, +#endif +#if 0 + CPU_POWERPC_405S = xxx, +#endif + /* IBM network processors */ + CPU_POWERPC_NPE405H = 0x414100C0, + CPU_POWERPC_NPE405H2 = 0x41410140, + CPU_POWERPC_NPE405L = 0x416100C0, + CPU_POWERPC_NPE4GS3 = 0x40B10000, +#if 0 + CPU_POWERPC_NPCxx1 = xxx, +#endif +#if 0 + CPU_POWERPC_NPR161 = xxx, +#endif +#if 0 + CPU_POWERPC_LC77700 = xxx, +#endif + /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ +#if 0 + CPU_POWERPC_STB01000 = xxx, +#endif +#if 0 + CPU_POWERPC_STB01010 = xxx, +#endif +#if 0 + CPU_POWERPC_STB0210 = xxx, /* 401B3 */ +#endif + CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */ +#if 0 + CPU_POWERPC_STB043 = xxx, +#endif +#if 0 + CPU_POWERPC_STB045 = xxx, +#endif + CPU_POWERPC_STB04 = 0x41810000, + CPU_POWERPC_STB25 = 0x51510950, +#if 0 + CPU_POWERPC_STB130 = xxx, +#endif + /* Xilinx cores */ + CPU_POWERPC_X2VP4 = 0x20010820, +#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4 + CPU_POWERPC_X2VP20 = 0x20010860, +#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20 +#if 0 + CPU_POWERPC_ZL10310 = xxx, +#endif +#if 0 + CPU_POWERPC_ZL10311 = xxx, +#endif +#if 0 + CPU_POWERPC_ZL10320 = xxx, +#endif +#if 0 + CPU_POWERPC_ZL10321 = xxx, +#endif + /* PowerPC 440 family */ + /* Generic PowerPC 440 */ +#define CPU_POWERPC_440 CPU_POWERPC_440GXf + /* PowerPC 440 cores */ +#if 0 + CPU_POWERPC_440A4 = xxx, +#endif +#if 0 + CPU_POWERPC_440A5 = xxx, +#endif +#if 0 + CPU_POWERPC_440B4 = xxx, +#endif +#if 0 + CPU_POWERPC_440F5 = xxx, +#endif +#if 0 + CPU_POWERPC_440G5 = xxx, +#endif +#if 0 + CPU_POWERPC_440H4 = xxx, +#endif +#if 0 + CPU_POWERPC_440H6 = xxx, +#endif + /* PowerPC 440 microcontrolers */ +#define CPU_POWERPC_440EP CPU_POWERPC_440EPb + CPU_POWERPC_440EPa = 0x42221850, + CPU_POWERPC_440EPb = 0x422218D3, +#define CPU_POWERPC_440GP CPU_POWERPC_440GPc + CPU_POWERPC_440GPb = 0x40120440, + CPU_POWERPC_440GPc = 0x40120481, +#define CPU_POWERPC_440GR CPU_POWERPC_440GRa +#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb + CPU_POWERPC_440GRX = 0x200008D0, +#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX +#define CPU_POWERPC_440GX CPU_POWERPC_440GXf + CPU_POWERPC_440GXa = 0x51B21850, + CPU_POWERPC_440GXb = 0x51B21851, + CPU_POWERPC_440GXc = 0x51B21892, + CPU_POWERPC_440GXf = 0x51B21894, +#if 0 + CPU_POWERPC_440S = xxx, +#endif + CPU_POWERPC_440SP = 0x53221850, + CPU_POWERPC_440SP2 = 0x53221891, + CPU_POWERPC_440SPE = 0x53421890, + /* PowerPC 460 family */ +#if 0 + /* Generic PowerPC 464 */ +#define CPU_POWERPC_464 CPU_POWERPC_464H90 +#endif + /* PowerPC 464 microcontrolers */ +#if 0 + CPU_POWERPC_464H90 = xxx, +#endif +#if 0 + CPU_POWERPC_464H90FP = xxx, +#endif + /* Freescale embedded PowerPC cores */ + /* e200 family */ +#define CPU_POWERPC_e200 CPU_POWERPC_e200z6 +#if 0 + CPU_POWERPC_e200z0 = xxx, +#endif +#if 0 + CPU_POWERPC_e200z3 = xxx, +#endif + CPU_POWERPC_e200z5 = 0x81000000, + CPU_POWERPC_e200z6 = 0x81120000, + /* e300 family */ +#define CPU_POWERPC_e300 CPU_POWERPC_e300c3 + CPU_POWERPC_e300c1 = 0x00830000, + CPU_POWERPC_e300c2 = 0x00840000, + CPU_POWERPC_e300c3 = 0x00850000, + /* e500 family */ +#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22 + CPU_POWERPC_e500_v11 = 0x80200010, + CPU_POWERPC_e500_v12 = 0x80200020, + CPU_POWERPC_e500_v21 = 0x80210010, + CPU_POWERPC_e500_v22 = 0x80210020, +#if 0 + CPU_POWERPC_e500mc = xxx, +#endif + /* e600 family */ + CPU_POWERPC_e600 = 0x80040010, + /* PowerPC MPC 5xx cores */ + CPU_POWERPC_5xx = 0x00020020, + /* PowerPC MPC 8xx cores (aka PowerQUICC) */ + CPU_POWERPC_8xx = 0x00500000, + /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */ + CPU_POWERPC_82xx_HIP3 = 0x00810101, + CPU_POWERPC_82xx_HIP4 = 0x80811014, + CPU_POWERPC_827x = 0x80822013, + /* PowerPC 6xx cores */ + CPU_POWERPC_601 = 0x00010001, + CPU_POWERPC_601a = 0x00010002, + CPU_POWERPC_602 = 0x00050100, + CPU_POWERPC_603 = 0x00030100, +#define CPU_POWERPC_603E CPU_POWERPC_603E_v41 + CPU_POWERPC_603E_v11 = 0x00060101, + CPU_POWERPC_603E_v12 = 0x00060102, + CPU_POWERPC_603E_v13 = 0x00060103, + CPU_POWERPC_603E_v14 = 0x00060104, + CPU_POWERPC_603E_v22 = 0x00060202, + CPU_POWERPC_603E_v3 = 0x00060300, + CPU_POWERPC_603E_v4 = 0x00060400, + CPU_POWERPC_603E_v41 = 0x00060401, + CPU_POWERPC_603E7t = 0x00071201, + CPU_POWERPC_603E7v = 0x00070100, + CPU_POWERPC_603E7v1 = 0x00070101, + CPU_POWERPC_603E7v2 = 0x00070201, + CPU_POWERPC_603E7 = 0x00070200, + CPU_POWERPC_603P = 0x00070000, +#define CPU_POWERPC_603R CPU_POWERPC_603E7t + CPU_POWERPC_G2 = 0x00810011, +#if 0 // Linux pretends the MSB is zero... + CPU_POWERPC_G2H4 = 0x80811010, + CPU_POWERPC_G2gp = 0x80821010, + CPU_POWERPC_G2ls = 0x90810010, + CPU_POWERPC_G2LE = 0x80820010, + CPU_POWERPC_G2LEgp = 0x80822010, + CPU_POWERPC_G2LEls = 0xA0822010, +#else + CPU_POWERPC_G2H4 = 0x00811010, + CPU_POWERPC_G2gp = 0x00821010, + CPU_POWERPC_G2ls = 0x10810010, + CPU_POWERPC_G2LE = 0x00820010, + CPU_POWERPC_G2LEgp = 0x00822010, + CPU_POWERPC_G2LEls = 0x20822010, +#endif + CPU_POWERPC_604 = 0x00040103, +#define CPU_POWERPC_604E CPU_POWERPC_604E_v24 + CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */ + CPU_POWERPC_604E_v22 = 0x00090202, + CPU_POWERPC_604E_v24 = 0x00090204, + CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */ +#if 0 + CPU_POWERPC_604EV = xxx, +#endif + /* PowerPC 740/750 cores (aka G3) */ + /* XXX: missing 0x00084202 */ +#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31 + CPU_POWERPC_7x0_v20 = 0x00080200, + CPU_POWERPC_7x0_v21 = 0x00080201, + CPU_POWERPC_7x0_v22 = 0x00080202, + CPU_POWERPC_7x0_v30 = 0x00080300, + CPU_POWERPC_7x0_v31 = 0x00080301, + CPU_POWERPC_740E = 0x00080100, + CPU_POWERPC_7x0P = 0x10080000, + /* XXX: missing 0x00087010 (CL ?) */ + CPU_POWERPC_750CL = 0x00087200, +#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22 + CPU_POWERPC_750CX_v21 = 0x00082201, + CPU_POWERPC_750CX_v22 = 0x00082202, +#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b + CPU_POWERPC_750CXE_v21 = 0x00082211, + CPU_POWERPC_750CXE_v22 = 0x00082212, + CPU_POWERPC_750CXE_v23 = 0x00082213, + CPU_POWERPC_750CXE_v24 = 0x00082214, + CPU_POWERPC_750CXE_v24b = 0x00083214, + CPU_POWERPC_750CXE_v31 = 0x00083211, + CPU_POWERPC_750CXE_v31b = 0x00083311, + CPU_POWERPC_750CXR = 0x00083410, + CPU_POWERPC_750E = 0x00080200, + CPU_POWERPC_750FL = 0x700A0203, +#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23 + CPU_POWERPC_750FX_v10 = 0x70000100, + CPU_POWERPC_750FX_v20 = 0x70000200, + CPU_POWERPC_750FX_v21 = 0x70000201, + CPU_POWERPC_750FX_v22 = 0x70000202, + CPU_POWERPC_750FX_v23 = 0x70000203, + CPU_POWERPC_750GL = 0x70020102, +#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12 + CPU_POWERPC_750GX_v10 = 0x70020100, + CPU_POWERPC_750GX_v11 = 0x70020101, + CPU_POWERPC_750GX_v12 = 0x70020102, +#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */ + CPU_POWERPC_750L_v22 = 0x00088202, + CPU_POWERPC_750L_v30 = 0x00088300, + CPU_POWERPC_750L_v32 = 0x00088302, + /* PowerPC 745/755 cores */ +#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28 + CPU_POWERPC_7x5_v10 = 0x00083100, + CPU_POWERPC_7x5_v11 = 0x00083101, + CPU_POWERPC_7x5_v20 = 0x00083200, + CPU_POWERPC_7x5_v21 = 0x00083201, + CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */ + CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */ + CPU_POWERPC_7x5_v24 = 0x00083204, + CPU_POWERPC_7x5_v25 = 0x00083205, + CPU_POWERPC_7x5_v26 = 0x00083206, + CPU_POWERPC_7x5_v27 = 0x00083207, + CPU_POWERPC_7x5_v28 = 0x00083208, +#if 0 + CPU_POWERPC_7x5P = xxx, +#endif + /* PowerPC 74xx cores (aka G4) */ + /* XXX: missing 0x000C1101 */ +#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29 + CPU_POWERPC_7400_v10 = 0x000C0100, + CPU_POWERPC_7400_v11 = 0x000C0101, + CPU_POWERPC_7400_v20 = 0x000C0200, + CPU_POWERPC_7400_v22 = 0x000C0202, + CPU_POWERPC_7400_v26 = 0x000C0206, + CPU_POWERPC_7400_v27 = 0x000C0207, + CPU_POWERPC_7400_v28 = 0x000C0208, + CPU_POWERPC_7400_v29 = 0x000C0209, +#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14 + CPU_POWERPC_7410_v10 = 0x800C1100, + CPU_POWERPC_7410_v11 = 0x800C1101, + CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */ + CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */ + CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */ +#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21 + CPU_POWERPC_7448_v10 = 0x80040100, + CPU_POWERPC_7448_v11 = 0x80040101, + CPU_POWERPC_7448_v20 = 0x80040200, + CPU_POWERPC_7448_v21 = 0x80040201, +#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21 + CPU_POWERPC_7450_v10 = 0x80000100, + CPU_POWERPC_7450_v11 = 0x80000101, + CPU_POWERPC_7450_v12 = 0x80000102, + CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */ + CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */ + CPU_POWERPC_74x1 = 0x80000203, + CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */ + /* XXX: missing 0x80010200 */ +#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32 + CPU_POWERPC_74x5_v10 = 0x80010100, + CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */ + CPU_POWERPC_74x5_v32 = 0x80010302, + CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */ + CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */ +#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12 + CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */ + CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */ + CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */ + /* 64 bits PowerPC */ + CPU_POWERPC_620 = 0x00140000, + CPU_POWERPC_630 = 0x00400000, + CPU_POWERPC_631 = 0x00410104, + CPU_POWERPC_POWER4 = 0x00350000, + CPU_POWERPC_POWER4P = 0x00380000, + CPU_POWERPC_POWER5 = 0x003A0203, +#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5 + CPU_POWERPC_POWER5P = 0x003B0000, +#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P + CPU_POWERPC_POWER6 = 0x003E0000, + CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */ + CPU_POWERPC_POWER6A = 0x0F000002, + CPU_POWERPC_970 = 0x00390202, +#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31 + CPU_POWERPC_970FX_v10 = 0x00391100, + CPU_POWERPC_970FX_v20 = 0x003C0200, + CPU_POWERPC_970FX_v21 = 0x003C0201, + CPU_POWERPC_970FX_v30 = 0x003C0300, + CPU_POWERPC_970FX_v31 = 0x003C0301, + CPU_POWERPC_970GX = 0x00450000, +#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11 + CPU_POWERPC_970MP_v10 = 0x00440100, + CPU_POWERPC_970MP_v11 = 0x00440101, +#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32 + CPU_POWERPC_CELL_v10 = 0x00700100, + CPU_POWERPC_CELL_v20 = 0x00700400, + CPU_POWERPC_CELL_v30 = 0x00700500, + CPU_POWERPC_CELL_v31 = 0x00700501, +#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31 + CPU_POWERPC_RS64 = 0x00330000, + CPU_POWERPC_RS64II = 0x00340000, + CPU_POWERPC_RS64III = 0x00360000, + CPU_POWERPC_RS64IV = 0x00370000, + /* Original POWER */ + /* XXX: should be POWER (RIOS), RSC3308, RSC4608, + * POWER2 (RIOS2) & RSC2 (P2SC) here + */ +#if 0 + CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */ +#endif +#if 0 + CPU_POWER2 = xxx, /* 0x40000 ? */ +#endif + /* PA Semi core */ + CPU_POWERPC_PA6T = 0x00900000, +}; - case CPU_PPC_440EP: /* 440 EP family */ - case CPU_PPC_440GP: /* 440 GP family */ - case CPU_PPC_440GX: /* 440 GX family */ - case CPU_PPC_440GXc: /* 440 GXc family */ - case CPU_PPC_440GXf: /* 440 GXf family */ - case CPU_PPC_440SP: /* 440 SP family */ - case CPU_PPC_440SP2: - case CPU_PPC_440SPE: /* 440 SPE family */ - gen_spr_generic(env); - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env); - gen_spr_440(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* XXX: TODO: allocate internal IRQ controller */ - break; +/* System version register (used on MPC 8xxx) */ +enum { + PPC_SVR_8540 = 0x80300000, + PPC_SVR_8541E = 0x807A0010, + PPC_SVR_8543v10 = 0x80320010, + PPC_SVR_8543v11 = 0x80320011, + PPC_SVR_8543v20 = 0x80320020, + PPC_SVR_8543Ev10 = 0x803A0010, + PPC_SVR_8543Ev11 = 0x803A0011, + PPC_SVR_8543Ev20 = 0x803A0020, + PPC_SVR_8545 = 0x80310220, + PPC_SVR_8545E = 0x80390220, + PPC_SVR_8547E = 0x80390120, + PPC_SCR_8548v10 = 0x80310010, + PPC_SCR_8548v11 = 0x80310011, + PPC_SCR_8548v20 = 0x80310020, + PPC_SVR_8548Ev10 = 0x80390010, + PPC_SVR_8548Ev11 = 0x80390011, + PPC_SVR_8548Ev20 = 0x80390020, + PPC_SVR_8555E = 0x80790010, + PPC_SVR_8560v10 = 0x80700010, + PPC_SVR_8560v20 = 0x80700020, +}; - /* Embedded PowerPC from Freescale */ +/*****************************************************************************/ +/* PowerPC CPU definitions */ +#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \ + { \ + .name = _name, \ + .pvr = _pvr, \ + .pvr_mask = _pvr_mask, \ + .insns_flags = glue(POWERPC_INSNS_,_type), \ + .msr_mask = glue(POWERPC_MSRM_,_type), \ + .mmu_model = glue(POWERPC_MMU_,_type), \ + .excp_model = glue(POWERPC_EXCP_,_type), \ + .bus_model = glue(POWERPC_INPUT_,_type), \ + .init_proc = &glue(init_proc_,_type), \ + } + +static ppc_def_t ppc_defs[] = { + /* Embedded PowerPC */ + /* PowerPC 401 family */ + /* Generic PowerPC 401 */ + POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401), + /* PowerPC 401 cores */ + /* PowerPC 401A1 */ + POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401), + /* PowerPC 401B2 */ + POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2), #if defined (TODO) - case CPU_PPC_5xx: - break; + /* PowerPC 401B3 */ + POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3), #endif + /* PowerPC 401C2 */ + POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2), + /* PowerPC 401D2 */ + POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2), + /* PowerPC 401E2 */ + POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2), + /* PowerPC 401F2 */ + POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2), + /* PowerPC 401G2 */ + /* XXX: to be checked */ + POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2), + /* PowerPC 401 microcontrolers */ #if defined (TODO) - case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ - break; + /* PowerPC 401GF */ + POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401), #endif + /* IOP480 (401 microcontroler) */ + POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480), + /* IBM Processor for Network Resources */ + POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401), #if defined (TODO) - case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ - case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ - break; + POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401), #endif + /* PowerPC 403 family */ + /* Generic PowerPC 403 */ + POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403), + /* PowerPC 403 microcontrolers */ + /* PowerPC 403 GA */ + POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403), + /* PowerPC 403 GB */ + POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403), + /* PowerPC 403 GC */ + POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403), + /* PowerPC 403 GCX */ + POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX), #if defined (TODO) - case CPU_PPC_827x: /* MPC 827x / 828x */ - break; + /* PowerPC 403 GP */ + POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403), #endif - - /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */ - case CPU_PPC_e500v110: - case CPU_PPC_e500v120: - case CPU_PPC_e500v210: - case CPU_PPC_e500v220: - gen_spr_generic(env); - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env); - gen_spr_BookE_FSL(env); - env->nb_BATs = 0; - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - /* XXX: TODO: allocate internal IRQ controller */ - break; - + /* PowerPC 405 family */ + /* Generic PowerPC 405 */ + POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405), + /* PowerPC 405 cores */ #if defined (TODO) - case CPU_PPC_e600: - break; + /* PowerPC 405 A3 */ + POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405), #endif - - /* 32 bits PowerPC */ - case CPU_PPC_601: /* PowerPC 601 */ - gen_spr_generic(env); - gen_spr_ne_601(env); - gen_spr_601(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_601_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_601_HID5, "HID5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ -#if 0 /* ? */ - spr_register(env, SPR_601_HID15, "HID15", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); +#if defined (TODO) + /* PowerPC 405 A4 */ + POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405), #endif - env->nb_tlb = 64; - env->nb_ways = 2; - env->id_tlbs = 0; - env->id_tlbs = 0; - /* XXX: TODO: allocate internal IRQ controller */ - break; - - case CPU_PPC_602: /* PowerPC 602 */ - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - gen_spr_602(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_603: /* PowerPC 603 */ - case CPU_PPC_603E: /* PowerPC 603e */ - case CPU_PPC_603E7v: - case CPU_PPC_603E7v2: - case CPU_PPC_603P: /* PowerPC 603p */ - case CPU_PPC_603R: /* PowerPC 603r */ - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - gen_spr_603(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_G2: /* PowerPC G2 family */ - case CPU_PPC_G2H4: - case CPU_PPC_G2gp: - case CPU_PPC_G2ls: - case CPU_PPC_G2LE: /* PowerPC G2LE family */ - case CPU_PPC_G2LEgp: - case CPU_PPC_G2LEls: - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - /* Memory management */ - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - gen_spr_G2_755(env); - gen_spr_G2(env); - /* Hardware implementation register */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_604: /* PowerPC 604 */ - case CPU_PPC_604E: /* PowerPC 604e */ - case CPU_PPC_604R: /* PowerPC 604r */ - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - gen_spr_604(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_74x: /* PowerPC 740 / 750 */ - case CPU_PPC_740E: - case CPU_PPC_750E: - case CPU_PPC_74xP: /* PowerPC 740P / 750P */ - case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ - case CPU_PPC_750CXE22: - case CPU_PPC_750CXE23: - case CPU_PPC_750CXE24: - case CPU_PPC_750CXE24b: - case CPU_PPC_750CXE31: - case CPU_PPC_750CXE31b: - case CPU_PPC_750CXR: - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - gen_spr_7xx(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ - case CPU_PPC_750FX20: - case CPU_PPC_750FX21: - case CPU_PPC_750FX22: - case CPU_PPC_750FX23: - case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ - case CPU_PPC_750GX11: - case CPU_PPC_750GX12: - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ - gen_high_BATs(env); - /* Time base */ - gen_tbl(env); - gen_spr_7xx(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - - case CPU_PPC_755_10: /* PowerPC 755 */ - case CPU_PPC_755_11: - case CPU_PPC_755_20: - case CPU_PPC_755D: - case CPU_PPC_755E: - gen_spr_generic(env); - gen_spr_ne_601(env); - /* Memory management */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - /* Memory management */ - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - gen_spr_G2_755(env); - /* L2 cache control */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTC, "ICTC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_L2PM, "L2PM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); - break; - #if defined (TODO) - /* G4 family */ - case CPU_PPC_7400: /* PowerPC 7400 */ - case CPU_PPC_7410C: /* PowerPC 7410 */ - case CPU_PPC_7410D: - case CPU_PPC_7410E: - case CPU_PPC_7441: /* PowerPC 7441 */ - case CPU_PPC_7445: /* PowerPC 7445 */ - case CPU_PPC_7447: /* PowerPC 7447 */ - case CPU_PPC_7447A: /* PowerPC 7447A */ - case CPU_PPC_7448: /* PowerPC 7448 */ - case CPU_PPC_7450: /* PowerPC 7450 */ - case CPU_PPC_7450b: - case CPU_PPC_7451: /* PowerPC 7451 */ - case CPU_PPC_7451G: - case CPU_PPC_7455: /* PowerPC 7455 */ - case CPU_PPC_7455F: - case CPU_PPC_7455G: - case CPU_PPC_7457: /* PowerPC 7457 */ - case CPU_PPC_7457C: - case CPU_PPC_7457A: /* PowerPC 7457A */ - break; + /* PowerPC 405 B3 */ + POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 B4 */ + POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 C3 */ + POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 C4 */ + POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 D2 */ + POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405), +#if defined (TODO) + /* PowerPC 405 D3 */ + POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 D4 */ + POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405), +#if defined (TODO) + /* PowerPC 405 D5 */ + POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 E4 */ + POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 F4 */ + POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 F5 */ + POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC 405 F6 */ + POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 microcontrolers */ + /* PowerPC 405 CR */ + POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405), + /* PowerPC 405 CRa */ + POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405), + /* PowerPC 405 CRb */ + POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405), + /* PowerPC 405 CRc */ + POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405), + /* PowerPC 405 EP */ + POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405), +#if defined(TODO) + /* PowerPC 405 EXr */ + POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 EZ */ + POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405), +#if defined(TODO) + /* PowerPC 405 FX */ + POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 GP */ + POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405), + /* PowerPC 405 GPa */ + POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405), + /* PowerPC 405 GPb */ + POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405), + /* PowerPC 405 GPc */ + POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405), + /* PowerPC 405 GPd */ + POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405), + /* PowerPC 405 GPe */ + POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405), + /* PowerPC 405 GPR */ + POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405), +#if defined(TODO) + /* PowerPC 405 H */ + POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405), +#endif +#if defined(TODO) + /* PowerPC 405 L */ + POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405), +#endif + /* PowerPC 405 LP */ + POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405), +#if defined(TODO) + /* PowerPC 405 PM */ + POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405), +#endif +#if defined(TODO) + /* PowerPC 405 PS */ + POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405), +#endif +#if defined(TODO) + /* PowerPC 405 S */ + POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405), +#endif + /* Npe405 H */ + POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405), + /* Npe405 H2 */ + POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405), + /* Npe405 L */ + POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405), + /* Npe4GS3 */ + POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405), +#if defined (TODO) + POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* PowerPC LC77700 (Sanyo) */ + POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405), +#endif + /* PowerPC 401/403/405 based set-top-box microcontrolers */ +#if defined (TODO) + /* STB010000 */ + POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2), +#endif +#if defined (TODO) + /* STB01010 */ + POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2), +#endif +#if defined (TODO) + /* STB0210 */ + POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3), +#endif + /* STB03xx */ + POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405), +#if defined (TODO) + /* STB043x */ + POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* STB045x */ + POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405), +#endif + /* STB04xx */ + POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405), + /* STB25xx */ + POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405), +#if defined (TODO) + /* STB130 */ + POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405), +#endif + /* Xilinx PowerPC 405 cores */ + POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405), + POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405), + POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405), + POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405), +#if defined (TODO) + /* Zarlink ZL10310 */ + POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* Zarlink ZL10311 */ + POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* Zarlink ZL10320 */ + POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405), +#endif +#if defined (TODO) + /* Zarlink ZL10321 */ + POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405), +#endif + /* PowerPC 440 family */ + /* Generic PowerPC 440 */ + POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP), + /* PowerPC 440 cores */ +#if defined (TODO) + /* PowerPC 440 A4 */ + POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4), +#endif +#if defined (TODO) + /* PowerPC 440 A5 */ + POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5), +#endif +#if defined (TODO) + /* PowerPC 440 B4 */ + POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4), +#endif +#if defined (TODO) + /* PowerPC 440 G4 */ + POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4), +#endif +#if defined (TODO) + /* PowerPC 440 F5 */ + POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5), +#endif +#if defined (TODO) + /* PowerPC 440 G5 */ + POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5), +#endif +#if defined (TODO) + /* PowerPC 440H4 */ + POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4), +#endif +#if defined (TODO) + /* PowerPC 440H6 */ + POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5), +#endif + /* PowerPC 440 microcontrolers */ + /* PowerPC 440 EP */ + POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP), + /* PowerPC 440 EPa */ + POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP), + /* PowerPC 440 EPb */ + POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP), + /* PowerPC 440 EPX */ + POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP), + /* PowerPC 440 GP */ + POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP), + /* PowerPC 440 GPb */ + POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP), + /* PowerPC 440 GPc */ + POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP), + /* PowerPC 440 GR */ + POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5), + /* PowerPC 440 GRa */ + POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5), + /* PowerPC 440 GRX */ + POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5), + /* PowerPC 440 GX */ + POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP), + /* PowerPC 440 GXa */ + POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP), + /* PowerPC 440 GXb */ + POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP), + /* PowerPC 440 GXc */ + POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP), + /* PowerPC 440 GXf */ + POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP), +#if defined(TODO) + /* PowerPC 440 S */ + POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440), +#endif + /* PowerPC 440 SP */ + POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP), + /* PowerPC 440 SP2 */ + POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP), + /* PowerPC 440 SPE */ + POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP), + /* PowerPC 460 family */ +#if defined (TODO) + /* Generic PowerPC 464 */ + POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460), +#endif + /* PowerPC 464 microcontrolers */ +#if defined (TODO) + /* PowerPC 464H90 */ + POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460), +#endif +#if defined (TODO) + /* PowerPC 464H90F */ + POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F), +#endif + /* Freescale embedded PowerPC cores */ + /* e200 family */ +#if defined (TODO) + /* Generic PowerPC e200 core */ + POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200), +#endif +#if defined (TODO) + /* PowerPC e200z5 core */ + POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200), +#endif +#if defined (TODO) + /* PowerPC e200z6 core */ + POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200), +#endif + /* e300 family */ +#if defined (TODO) + /* Generic PowerPC e300 core */ + POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300), +#endif +#if defined (TODO) + /* PowerPC e300c1 core */ + POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300), +#endif +#if defined (TODO) + /* PowerPC e300c2 core */ + POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300), +#endif +#if defined (TODO) + /* PowerPC e300c3 core */ + POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300), +#endif + /* e500 family */ +#if defined (TODO) + /* PowerPC e500 core */ + POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500), +#endif +#if defined (TODO) + /* PowerPC e500 v1.1 core */ + POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500), +#endif +#if defined (TODO) + /* PowerPC e500 v1.2 core */ + POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500), +#endif +#if defined (TODO) + /* PowerPC e500 v2.1 core */ + POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500), +#endif +#if defined (TODO) + /* PowerPC e500 v2.2 core */ + POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500), +#endif + /* e600 family */ +#if defined (TODO) + /* PowerPC e600 core */ + POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600), +#endif + /* PowerPC MPC 5xx cores */ +#if defined (TODO) + /* PowerPC MPC 5xx */ + POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx), +#endif + /* PowerPC MPC 8xx cores */ +#if defined (TODO) + /* PowerPC MPC 8xx */ + POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx), +#endif + /* PowerPC MPC 8xxx cores */ +#if defined (TODO) + /* PowerPC MPC 82xx HIP3 */ + POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx), +#endif +#if defined (TODO) + /* PowerPC MPC 82xx HIP4 */ + POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx), +#endif +#if defined (TODO) + /* PowerPC MPC 827x */ + POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x), #endif - /* 64 bits PowerPC */ + /* 32 bits "classic" PowerPC */ + /* PowerPC 6xx family */ + /* PowerPC 601 */ + POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601), + /* PowerPC 601v2 */ + POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601), + /* PowerPC 602 */ + POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602), + /* PowerPC 603 */ + POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603), + /* Code name for PowerPC 603 */ + POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603), + /* PowerPC 603e */ + POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E), + /* Code name for PowerPC 603e */ + POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E), + /* PowerPC 603e v1.1 */ + POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E), + /* PowerPC 603e v1.2 */ + POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E), + /* PowerPC 603e v1.3 */ + POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E), + /* PowerPC 603e v1.4 */ + POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E), + /* PowerPC 603e v2.2 */ + POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E), + /* PowerPC 603e v3 */ + POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E), + /* PowerPC 603e v4 */ + POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E), + /* PowerPC 603e v4.1 */ + POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E), + /* PowerPC 603e */ + POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E), + /* PowerPC 603e7t */ + POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E), + /* PowerPC 603e7v */ + POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E), + /* Code name for PowerPC 603ev */ + POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E), + /* PowerPC 603e7v1 */ + POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E), + /* PowerPC 603e7v2 */ + POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E), + /* PowerPC 603p */ + /* to be checked */ + POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603), + /* PowerPC 603r */ + POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E), + /* Code name for PowerPC 603r */ + POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E), + /* PowerPC G2 core */ + POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2), + /* PowerPC G2 H4 */ + POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2), + /* PowerPC G2 GP */ + POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2), + /* PowerPC G2 LS */ + POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2), + /* PowerPC G2LE */ + /* Same as G2, with little-endian mode support */ + POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE), + /* PowerPC G2LE GP */ + POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE), + /* PowerPC G2LE LS */ + POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE), + /* PowerPC 604 */ + POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604), + /* PowerPC 604e */ + POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604), + /* PowerPC 604e v1.0 */ + POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604), + /* PowerPC 604e v2.2 */ + POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604), + /* PowerPC 604e v2.4 */ + POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604), + /* PowerPC 604r */ + POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604), +#if defined(TODO) + /* PowerPC 604ev */ + POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604), +#endif + /* PowerPC 7xx family */ + /* Generic PowerPC 740 (G3) */ + POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0), + /* Generic PowerPC 750 (G3) */ + POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0), + /* Code name for generic PowerPC 740/750 (G3) */ + POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0), + /* PowerPC 740/750 is also known as G3 */ + POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0), + /* PowerPC 740 v2.0 (G3) */ + POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0), + /* PowerPC 750 v2.0 (G3) */ + POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0), + /* PowerPC 740 v2.1 (G3) */ + POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0), + /* PowerPC 750 v2.1 (G3) */ + POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0), + /* PowerPC 740 v2.2 (G3) */ + POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0), + /* PowerPC 750 v2.2 (G3) */ + POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0), + /* PowerPC 740 v3.0 (G3) */ + POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0), + /* PowerPC 750 v3.0 (G3) */ + POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0), + /* PowerPC 740 v3.1 (G3) */ + POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0), + /* PowerPC 750 v3.1 (G3) */ + POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0), + /* PowerPC 740E (G3) */ + POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0), + /* PowerPC 740P (G3) */ + POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0), + /* PowerPC 750P (G3) */ + POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0), + /* Code name for PowerPC 740P/750P (G3) */ + POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0), + /* PowerPC 750CL (G3 embedded) */ + POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0), + /* PowerPC 750CX (G3 embedded) */ + POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0), + /* PowerPC 750CX v2.1 (G3 embedded) */ + POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0), + /* PowerPC 750CX v2.2 (G3 embedded) */ + POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe (G3 embedded) */ + POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v2.1 (G3 embedded) */ + POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v2.2 (G3 embedded) */ + POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v2.3 (G3 embedded) */ + POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v2.4 (G3 embedded) */ + POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v2.4b (G3 embedded) */ + POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v3.1 (G3 embedded) */ + POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXe v3.1b (G3 embedded) */ + POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0), + /* PowerPC 750CXr (G3 embedded) */ + POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0), + /* PowerPC 750E (G3) */ + POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0), + /* PowerPC 750FL (G3 embedded) */ + POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 7x0), + /* PowerPC 750FX (G3 embedded) */ + POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx), + /* PowerPC 750FX v1.0 (G3 embedded) */ + POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx), + /* PowerPC 750FX v2.0 (G3 embedded) */ + POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx), + /* PowerPC 750FX v2.1 (G3 embedded) */ + POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx), + /* PowerPC 750FX v2.2 (G3 embedded) */ + POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx), + /* PowerPC 750FX v2.3 (G3 embedded) */ + POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx), + /* PowerPC 750GL (G3 embedded) */ + POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 7x0), + /* PowerPC 750GX (G3 embedded) */ + POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx), + /* PowerPC 750GX v1.0 (G3 embedded) */ + POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx), + /* PowerPC 750GX v1.1 (G3 embedded) */ + POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx), + /* PowerPC 750GX v1.2 (G3 embedded) */ + POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx), + /* PowerPC 750L (G3 embedded) */ + POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0), + /* Code name for PowerPC 750L (G3 embedded) */ + POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0), + /* PowerPC 750L v2.2 (G3 embedded) */ + POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0), + /* PowerPC 750L v3.0 (G3 embedded) */ + POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0), + /* PowerPC 750L v3.2 (G3 embedded) */ + POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0), + /* Generic PowerPC 745 */ + POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5), + /* Generic PowerPC 755 */ + POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5), + /* Code name for PowerPC 745/755 */ + POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v1.0 */ + POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v1.0 */ + POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v1.1 */ + POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v1.1 */ + POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.0 */ + POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.0 */ + POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.1 */ + POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.1 */ + POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.2 */ + POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.2 */ + POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.3 */ + POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.3 */ + POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.4 */ + POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.4 */ + POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.5 */ + POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.5 */ + POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.6 */ + POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.6 */ + POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.7 */ + POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.7 */ + POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5), + /* PowerPC 745 v2.8 */ + POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5), + /* PowerPC 755 v2.8 */ + POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5), +#if defined (TODO) + /* PowerPC 745P (G3) */ + POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5), + /* PowerPC 755P (G3) */ + POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5), +#endif + /* PowerPC 74xx family */ + /* PowerPC 7400 (G4) */ + POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400), + /* Code name for PowerPC 7400 */ + POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400), + /* PowerPC 74xx is also well known as G4 */ + POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v1.0 (G4) */ + POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v1.1 (G4) */ + POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.0 (G4) */ + POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.2 (G4) */ + POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.6 (G4) */ + POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.7 (G4) */ + POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.8 (G4) */ + POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400), + /* PowerPC 7400 v2.9 (G4) */ + POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400), + /* PowerPC 7410 (G4) */ + POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410), + /* Code name for PowerPC 7410 */ + POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410), + /* PowerPC 7410 v1.0 (G4) */ + POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410), + /* PowerPC 7410 v1.1 (G4) */ + POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410), + /* PowerPC 7410 v1.2 (G4) */ + POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410), + /* PowerPC 7410 v1.3 (G4) */ + POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410), + /* PowerPC 7410 v1.4 (G4) */ + POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410), + /* PowerPC 7448 (G4) */ + POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400), + /* PowerPC 7448 v1.0 (G4) */ + POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400), + /* PowerPC 7448 v1.1 (G4) */ + POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400), + /* PowerPC 7448 v2.0 (G4) */ + POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400), + /* PowerPC 7448 v2.1 (G4) */ + POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400), +#if defined (TODO) + /* PowerPC 7450 (G4) */ + POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450), + /* Code name for PowerPC 7450 */ + POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7450 v1.0 (G4) */ + POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7450 v1.1 (G4) */ + POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7450 v1.2 (G4) */ + POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7450 v2.0 (G4) */ + POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7450 v2.1 (G4) */ + POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7441 (G4) */ + POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440), + /* PowerPC 7451 (G4) */ + POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7441g (G4) */ + POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440), + /* PowerPC 7451g (G4) */ + POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450), +#endif +#if defined (TODO) + /* PowerPC 7445 (G4) */ + POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445), + /* PowerPC 7455 (G4) */ + POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455), + /* Code name for PowerPC 7445/7455 */ + POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7445 v1.0 (G4) */ + POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445), + /* PowerPC 7455 v1.0 (G4) */ + POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7445 v2.1 (G4) */ + POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445), + /* PowerPC 7455 v2.1 (G4) */ + POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7445 v3.2 (G4) */ + POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445), + /* PowerPC 7455 v3.2 (G4) */ + POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7445 v3.3 (G4) */ + POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445), + /* PowerPC 7455 v3.3 (G4) */ + POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7445 v3.4 (G4) */ + POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445), + /* PowerPC 7455 v3.4 (G4) */ + POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7447 (G4) */ + POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445), + /* PowerPC 7457 (G4) */ + POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455), + /* Code name for PowerPC 7447/7457 */ + POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7447 v1.0 (G4) */ + POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445), + /* PowerPC 7457 v1.0 (G4) */ + POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455), + /* Code name for PowerPC 7447A/7457A */ + POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7447 v1.1 (G4) */ + POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445), + /* PowerPC 7457 v1.1 (G4) */ + POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455), +#endif +#if defined (TODO) + /* PowerPC 7447 v1.2 (G4) */ + POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445), + /* PowerPC 7457 v1.2 (G4) */ + POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455), +#endif + /* 64 bits PowerPC */ #if defined (TARGET_PPC64) #if defined (TODO) - case CPU_PPC_620: /* PowerPC 620 */ - case CPU_PPC_630: /* PowerPC 630 (Power 3) */ - case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ - case CPU_PPC_POWER4: /* Power 4 */ - case CPU_PPC_POWER4P: /* Power 4+ */ - case CPU_PPC_POWER5: /* Power 5 */ - case CPU_PPC_POWER5P: /* Power 5+ */ + /* PowerPC 620 */ + POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620), #endif - break; - - case CPU_PPC_970: /* PowerPC 970 */ - case CPU_PPC_970FX10: /* PowerPC 970 FX */ - case CPU_PPC_970FX20: - case CPU_PPC_970FX21: - case CPU_PPC_970FX30: - case CPU_PPC_970FX31: - case CPU_PPC_970MP10: /* PowerPC 970 MP */ - case CPU_PPC_970MP11: - gen_spr_generic(env); - gen_spr_ne_601(env); - /* XXX: not correct */ - gen_low_BATs(env); - /* Time base */ - gen_tbl(env); - gen_spr_7xx(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Allocate hardware IRQ controller */ - ppc970_irq_init(env); - break; - #if defined (TODO) - case CPU_PPC_CELL10: /* Cell family */ - case CPU_PPC_CELL20: - case CPU_PPC_CELL30: - case CPU_PPC_CELL31: + /* PowerPC 630 (POWER3) */ + POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630), + POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630), #endif - break; - #if defined (TODO) - case CPU_PPC_RS64: /* Apache (RS64/A35) */ - case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ - case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ - case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ + /* PowerPC 631 (Power 3+) */ + POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631), + POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631), +#endif +#if defined (TODO) + /* POWER4 */ + POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4), +#endif +#if defined (TODO) + /* POWER4p */ + POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P), +#endif +#if defined (TODO) + /* POWER5 */ + POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5), + /* POWER5GR */ + POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5), +#endif +#if defined (TODO) + /* POWER5+ */ + POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P), + /* POWER5GS */ + POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P), +#endif +#if defined (TODO) + /* POWER6 */ + POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6), + /* POWER6 running in POWER5 mode */ + POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5), + /* POWER6A */ + POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6), +#endif +#if defined (TODO) + /* PowerPC 970 */ + POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC 970FX (G5) */ + POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970FX v1.0 (G5) */ + POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970FX v2.0 (G5) */ + POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970FX v2.1 (G5) */ + POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970FX v3.0 (G5) */ + POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970FX v3.1 (G5) */ + POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX), +#endif +#if defined (TODO) + /* PowerPC 970GX (G5) */ + POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX), +#endif +#if defined (TODO) + /* PowerPC 970MP */ + POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC 970MP v1.0 */ + POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC 970MP v1.1 */ + POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell */ + POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell v1.0 */ + POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell v2.0 */ + POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell v3.0 */ + POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell v3.1 */ + POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* PowerPC Cell v3.2 */ + POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970), +#endif +#if defined (TODO) + /* RS64 (Apache/A35) */ + /* This one seems to support the whole POWER2 instruction set + * and the PowerPC 64 one. + */ + /* What about A10 & A30 ? */ + POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64), + POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64), + POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64), +#endif +#if defined (TODO) + /* RS64-II (NorthStar/A50) */ + POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64), + POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64), + POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64), +#endif +#if defined (TODO) + /* RS64-III (Pulsar) */ + POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64), + POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64), +#endif +#if defined (TODO) + /* RS64-IV (IceStar/IStar/SStar) */ + POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64), + POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64), + POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64), + POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64), #endif - break; #endif /* defined (TARGET_PPC64) */ - + /* POWER */ #if defined (TODO) - /* POWER */ - case CPU_POWER: /* POWER */ - case CPU_POWER2: /* POWER2 */ - break; + /* Original POWER */ + POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER), + POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER), + POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER), + POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER), + POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER), +#endif +#if defined (TODO) + /* POWER2 */ + POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER), + POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER), + POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER), +#endif + /* PA semi cores */ +#if defined (TODO) + /* PA PA6T */ + POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T), +#endif + /* Generic PowerPCs */ +#if defined (TARGET_PPC64) +#if defined (TODO) + POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64), #endif +#endif + POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32), + /* Fallback */ + POWERPC_DEF("ppc", CPU_POWERPC_PPC, 0xFFFFFFFF, PPC), +}; - default: - gen_spr_generic(env); - /* XXX: TODO: allocate internal IRQ controller */ - break; - } - if (env->nb_BATs == -1) - env->nb_BATs = 4; +/*****************************************************************************/ +/* Generic CPU instanciation routine */ +static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) +{ +#if !defined(CONFIG_USER_ONLY) + env->irq_inputs = NULL; +#endif + /* Default MMU definitions */ + env->nb_BATs = 0; + env->nb_tlb = 0; + env->nb_ways = 0; + /* Register SPR common to all PowerPC implementations */ + gen_spr_generic(env); + spr_register(env, SPR_PVR, "PVR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + def->pvr); + /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ + (*def->init_proc)(env); /* Allocate TLBs buffer when needed */ if (env->nb_tlb != 0) { int nb_tlb = env->nb_tlb; @@ -2518,36 +5053,47 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) /* Pre-compute some useful values */ env->tlb_per_way = env->nb_tlb / env->nb_ways; } +#if !defined(CONFIG_USER_ONLY) + if (env->irq_inputs == NULL) { + fprintf(stderr, "WARNING: no internal IRQ controller registered.\n" + " Attempt Qemu to crash very soon !\n"); + } +#endif } #if defined(PPC_DUMP_CPU) -static void dump_sprs (CPUPPCState *env) +static void dump_ppc_sprs (CPUPPCState *env) { ppc_spr_t *spr; - uint32_t pvr = env->spr[SPR_PVR]; - uint32_t sr, sw, ur, uw; +#if !defined(CONFIG_USER_ONLY) + uint32_t sr, sw; +#endif + uint32_t ur, uw; int i, j, n; - printf("* SPRs for PVR=%08x\n", pvr); + printf("Special purpose registers:\n"); for (i = 0; i < 32; i++) { for (j = 0; j < 32; j++) { n = (i << 5) | j; spr = &env->spr_cb[n]; + uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; + ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; #if !defined(CONFIG_USER_ONLY) sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; -#else - sw = 0; - sr = 0; -#endif - uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; - ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; if (sw || sr || uw || ur) { printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", (i << 5) | j, (i << 5) | j, spr->name, sw ? 'w' : '-', sr ? 'r' : '-', uw ? 'w' : '-', ur ? 'r' : '-'); } +#else + if (uw || ur) { + printf("SPR: %4d (%03x) %-8s u%c%c\n", + (i << 5) | j, (i << 5) | j, spr->name, + uw ? 'w' : '-', ur ? 'r' : '-'); + } +#endif } } fflush(stdout); @@ -2737,11 +5283,6 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) opcode_t *opc, *start, *end; fill_new_table(env->opcodes, 0x40); -#if defined(PPC_DUMP_CPU) - printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64 - " %08x\n", - def->pvr, def->name, def->insns_flags, def->flags); -#endif if (&opc_start < &opc_end) { start = &opc_start; end = &opc_end; @@ -2757,25 +5298,6 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) opc->opc3); return -1; } -#if defined(PPC_DUMP_CPU) - if (opc1 != 0x00) { - if (opc->opc3 == 0xFF) { - if (opc->opc2 == 0xFF) { - printf("INSN: %02x -- -- (%02d ----) : %s\n", - opc->opc1, opc->opc1, opc->oname); - } else { - printf("INSN: %02x %02x -- (%02d %04d) : %s\n", - opc->opc1, opc->opc2, opc->opc1, opc->opc2, - opc->oname); - } - } else { - printf("INSN: %02x %02x %02x (%02d %04d) : %s\n", - opc->opc1, opc->opc2, opc->opc3, - opc->opc1, (opc->opc3 << 5) | opc->opc2, - opc->oname); - } - } -#endif } } fix_opcode_tables(env->opcodes); @@ -2785,1555 +5307,184 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) return 0; } +#if defined(PPC_DUMP_CPU) +static int dump_ppc_insns (CPUPPCState *env) +{ + opc_handler_t **table, *handler; + uint8_t opc1, opc2, opc3; + + printf("Instructions set:\n"); + /* opc1 is 6 bits long */ + for (opc1 = 0x00; opc1 < 0x40; opc1++) { + table = env->opcodes; + handler = table[opc1]; + if (is_indirect_opcode(handler)) { + /* opc2 is 5 bits long */ + for (opc2 = 0; opc2 < 0x20; opc2++) { + table = env->opcodes; + handler = env->opcodes[opc1]; + table = ind_table(handler); + handler = table[opc2]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + /* opc3 is 5 bits long */ + for (opc3 = 0; opc3 < 0x20; opc3++) { + handler = table[opc3]; + if (handler->handler != &gen_invalid) { + printf("INSN: %02x %02x %02x (%02d %04d) : %s\n", + opc1, opc2, opc3, opc1, (opc3 << 5) | opc2, + handler->oname); + } + } + } else { + if (handler->handler != &gen_invalid) { + printf("INSN: %02x %02x -- (%02d %04d) : %s\n", + opc1, opc2, opc1, opc2, handler->oname); + } + } + } + } else { + if (handler->handler != &gen_invalid) { + printf("INSN: %02x -- -- (%02d ----) : %s\n", + opc1, opc1, handler->oname); + } + } + } +} +#endif + int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def) { env->msr_mask = def->msr_mask; - env->flags = def->flags; + env->mmu_model = def->mmu_model; + env->excp_model = def->excp_model; + env->bus_model = def->bus_model; if (create_ppc_opcodes(env, def) < 0) return -1; init_ppc_proc(env, def); #if defined(PPC_DUMP_CPU) - dump_sprs(env); - if (env->tlb != NULL) { - printf("%d %s TLB in %d ways\n", env->nb_tlb, - env->id_tlbs ? "splitted" : "merged", env->nb_ways); + { + const unsigned char *mmu_model, *excp_model, *bus_model; + switch (env->mmu_model) { + case POWERPC_MMU_32B: + mmu_model = "PowerPC 32"; + break; + case POWERPC_MMU_64B: + mmu_model = "PowerPC 64"; + break; + case POWERPC_MMU_601: + mmu_model = "PowerPC 601"; + break; + case POWERPC_MMU_SOFT_6xx: + mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_74xx: + mmu_model = "PowerPC 74xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_4xx: + mmu_model = "PowerPC 4xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_4xx_Z: + mmu_model = "PowerPC 4xx with software driven TLBs " + "and zones protections"; + break; + case POWERPC_MMU_REAL_4xx: + mmu_model = "PowerPC 4xx real mode only"; + break; + case POWERPC_MMU_BOOKE: + mmu_model = "PowerPC BookE"; + break; + case POWERPC_MMU_BOOKE_FSL: + mmu_model = "PowerPC BookE FSL"; + break; + case POWERPC_MMU_64BRIDGE: + mmu_model = "PowerPC 64 bridge"; + break; + default: + mmu_model = "Unknown or invalid"; + break; + } + switch (env->excp_model) { + case POWERPC_EXCP_STD: + excp_model = "PowerPC"; + break; + case POWERPC_EXCP_40x: + excp_model = "PowerPC 40x"; + break; + case POWERPC_EXCP_601: + excp_model = "PowerPC 601"; + break; + case POWERPC_EXCP_602: + excp_model = "PowerPC 602"; + break; + case POWERPC_EXCP_603: + excp_model = "PowerPC 603"; + break; + case POWERPC_EXCP_603E: + excp_model = "PowerPC 603e"; + break; + case POWERPC_EXCP_604: + excp_model = "PowerPC 604"; + break; + case POWERPC_EXCP_7x0: + excp_model = "PowerPC 740/750"; + break; + case POWERPC_EXCP_7x5: + excp_model = "PowerPC 745/755"; + break; + case POWERPC_EXCP_74xx: + excp_model = "PowerPC 74xx"; + break; + case POWERPC_EXCP_970: + excp_model = "PowerPC 970"; + break; + case POWERPC_EXCP_BOOKE: + excp_model = "PowerPC BookE"; + break; + default: + excp_model = "Unknown or invalid"; + break; + } + switch (env->bus_model) { + case PPC_FLAGS_INPUT_6xx: + bus_model = "PowerPC 6xx"; + break; + case PPC_FLAGS_INPUT_BookE: + bus_model = "PowerPC BookE"; + break; + case PPC_FLAGS_INPUT_405: + bus_model = "PowerPC 405"; + break; + case PPC_FLAGS_INPUT_970: + bus_model = "PowerPC 970"; + break; + case PPC_FLAGS_INPUT_401: + bus_model = "PowerPC 401/403"; + break; + default: + bus_model = "Unknown or invalid"; + break; + } + printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" + " MMU model : %s\n", + def->name, def->pvr, def->msr_mask, mmu_model); + if (env->tlb != NULL) { + printf(" %d %s TLB in %d ways\n", + env->nb_tlb, env->id_tlbs ? "splitted" : "merged", + env->nb_ways); + } + printf(" Exceptions model : %s\n" + " Bus model : %s\n", + excp_model, bus_model); } + dump_ppc_insns(env); + dump_ppc_sprs(env); + fflush(stdout); #endif return 0; } -/*****************************************************************************/ -/* PowerPC CPU definitions */ -static ppc_def_t ppc_defs[] = { - /* Embedded PowerPC */ - /* Generic PowerPC 401 */ - { - .name = "401", - .pvr = CPU_PPC_401, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401A1 */ - { - .name = "401a1", - .pvr = CPU_PPC_401A1, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401B2 */ - { - .name = "401b2", - .pvr = CPU_PPC_401B2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#if defined (TODO) - /* PowerPC 401B3 */ - { - .name = "401b3", - .pvr = CPU_PPC_401B3, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#endif - /* PowerPC 401C2 */ - { - .name = "401c2", - .pvr = CPU_PPC_401C2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401D2 */ - { - .name = "401d2", - .pvr = CPU_PPC_401D2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401E2 */ - { - .name = "401e2", - .pvr = CPU_PPC_401E2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401F2 */ - { - .name = "401f2", - .pvr = CPU_PPC_401F2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, - /* PowerPC 401G2 */ - { - .name = "401g2", - .pvr = CPU_PPC_401G2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#if defined (TODO) - /* PowerPC 401G2 */ - { - .name = "401gf", - .pvr = CPU_PPC_401GF, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#endif -#if defined (TODO) - /* IOP480 (401 microcontroler) */ - { - .name = "iop480", - .pvr = CPU_PPC_IOP480, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#endif -#if defined (TODO) - /* IBM Processor for Network Resources */ - { - .name = "Cobra", - .pvr = CPU_PPC_COBRA, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_401, - .flags = PPC_FLAGS_401, - .msr_mask = 0x000FD201, - }, -#endif - /* Generic PowerPC 403 */ - { - .name = "403", - .pvr = CPU_PPC_403, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, - /* PowerPC 403 GA */ - { - .name = "403ga", - .pvr = CPU_PPC_403GA, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, - /* PowerPC 403 GB */ - { - .name = "403gb", - .pvr = CPU_PPC_403GB, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, - /* PowerPC 403 GC */ - { - .name = "403gc", - .pvr = CPU_PPC_403GC, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, - /* PowerPC 403 GCX */ - { - .name = "403gcx", - .pvr = CPU_PPC_403GCX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, -#if defined (TODO) - /* PowerPC 403 GP */ - { - .name = "403gp", - .pvr = CPU_PPC_403GP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_403, - .flags = PPC_FLAGS_403, - .msr_mask = 0x000000000007D23DULL, - }, -#endif - /* Generic PowerPC 405 */ - { - .name = "405", - .pvr = CPU_PPC_405, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#if defined (TODO) - /* PowerPC 405 A3 */ - { - .name = "405a3", - .pvr = CPU_PPC_405A3, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 405 A4 */ - { - .name = "405a4", - .pvr = CPU_PPC_405A4, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 405 B3 */ - { - .name = "405b3", - .pvr = CPU_PPC_405B3, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif - /* PowerPC 405 D2 */ - { - .name = "405d2", - .pvr = CPU_PPC_405D2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* PowerPC 405 D4 */ - { - .name = "405d4", - .pvr = CPU_PPC_405D4, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* PowerPC 405 CR */ - { - .name = "405cr", - .pvr = CPU_PPC_405CR, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* PowerPC 405 GP */ - { - .name = "405gp", - .pvr = CPU_PPC_405GP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* PowerPC 405 EP */ - { - .name = "405ep", - .pvr = CPU_PPC_405EP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000000ED630ULL, - }, -#if defined (TODO) - /* PowerPC 405 EZ */ - { - .name = "405ez", - .pvr = CPU_PPC_405EZ, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 405 GPR */ - { - .name = "405gpr", - .pvr = CPU_PPC_405GPR, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 405 LP */ - { - .name = "405lp", - .pvr = CPU_PPC_405EZ, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif - /* Npe405 H */ - { - .name = "Npe405H", - .pvr = CPU_PPC_NPE405H, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* Npe405 H2 */ - { - .name = "Npe405H2", - .pvr = CPU_PPC_NPE405H2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - /* Npe405 L */ - { - .name = "Npe405L", - .pvr = CPU_PPC_NPE405L, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#if defined (TODO) - /* PowerPC LP777000 */ - { - .name = "lp777000", - .pvr = CPU_PPC_LP777000, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB010000 */ - { - .name = "STB01000", - .pvr = CPU_PPC_STB01000, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB01010 */ - { - .name = "STB01010", - .pvr = CPU_PPC_STB01010, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB0210 */ - { - .name = "STB0210", - .pvr = CPU_PPC_STB0210, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB03xx */ - { - .name = "STB03", - .pvr = CPU_PPC_STB03, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB043x */ - { - .name = "STB043", - .pvr = CPU_PPC_STB043, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB045x */ - { - .name = "STB045", - .pvr = CPU_PPC_STB045, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) || 1 - /* STB25xx */ - { - .name = "STB25", - .pvr = CPU_PPC_STB25, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif -#if defined (TODO) - /* STB130 */ - { - .name = "STB130", - .pvr = CPU_PPC_STB130, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif - /* Xilinx PowerPC 405 cores */ -#if defined (TODO) - { - .name = "x2vp4", - .pvr = CPU_PPC_X2VP4, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - { - .name = "x2vp7", - .pvr = CPU_PPC_X2VP7, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - { - .name = "x2vp20", - .pvr = CPU_PPC_X2VP20, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, - { - .name = "x2vp50", - .pvr = CPU_PPC_X2VP50, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_405, - .flags = PPC_FLAGS_405, - .msr_mask = 0x00000000020EFF30ULL, - }, -#endif - /* PowerPC 440 EP */ - { - .name = "440ep", - .pvr = CPU_PPC_440EP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 GR */ - { - .name = "440gr", - .pvr = CPU_PPC_440GR, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 GP */ - { - .name = "440gp", - .pvr = CPU_PPC_440GP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, -#if defined (TODO) - /* PowerPC 440 GRX */ - { - .name = "440grx", - .pvr = CPU_PPC_440GRX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, -#endif - /* PowerPC 440 GX */ - { - .name = "440gx", - .pvr = CPU_PPC_440GX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 GXc */ - { - .name = "440gxc", - .pvr = CPU_PPC_440GXc, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 GXf */ - { - .name = "440gxf", - .pvr = CPU_PPC_440GXf, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 SP */ - { - .name = "440sp", - .pvr = CPU_PPC_440SP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 SP2 */ - { - .name = "440sp2", - .pvr = CPU_PPC_440SP2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 440 SPE */ - { - .name = "440spe", - .pvr = CPU_PPC_440SPE, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_440, - .flags = PPC_FLAGS_440, - .msr_mask = 0x000000000006D630ULL, - }, - /* Fake generic BookE PowerPC */ - { - .name = "BookE", - .pvr = CPU_PPC_e500, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_BOOKE, - .flags = PPC_FLAGS_BOOKE, - .msr_mask = 0x000000000006D630ULL, - }, - /* PowerPC 460 cores - TODO */ - /* PowerPC MPC 5xx cores - TODO */ - /* PowerPC MPC 8xx cores - TODO */ - /* PowerPC MPC 8xxx cores - TODO */ - /* e200 cores - TODO */ - /* e500 cores - TODO */ - /* e600 cores - TODO */ - - /* 32 bits "classic" PowerPC */ -#if defined (TODO) - /* PowerPC 601 */ - { - .name = "601", - .pvr = CPU_PPC_601, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_601, - .flags = PPC_FLAGS_601, - .msr_mask = 0x000000000000FD70ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 602 */ - { - .name = "602", - .pvr = CPU_PPC_602, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_602, - .flags = PPC_FLAGS_602, - .msr_mask = 0x0000000000C7FF73ULL, - }, -#endif - /* PowerPC 603 */ - { - .name = "603", - .pvr = CPU_PPC_603, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603e */ - { - .name = "603e", - .pvr = CPU_PPC_603E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - { - .name = "Stretch", - .pvr = CPU_PPC_603E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603p */ - { - .name = "603p", - .pvr = CPU_PPC_603P, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603e7 */ - { - .name = "603e7", - .pvr = CPU_PPC_603E7, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603e7v */ - { - .name = "603e7v", - .pvr = CPU_PPC_603E7v, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603e7v2 */ - { - .name = "603e7v2", - .pvr = CPU_PPC_603E7v2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - /* PowerPC 603r */ - { - .name = "603r", - .pvr = CPU_PPC_603R, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, - { - .name = "Goldeneye", - .pvr = CPU_PPC_603R, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_603, - .flags = PPC_FLAGS_603, - .msr_mask = 0x000000000007FF73ULL, - }, -#if defined (TODO) - /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */ - { - .name = "G2", - .pvr = CPU_PPC_G2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000006FFF2ULL, - }, - { - .name = "G2h4", - .pvr = CPU_PPC_G2H4, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000006FFF2ULL, - }, - { - .name = "G2gp", - .pvr = CPU_PPC_G2gp, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000006FFF2ULL, - }, - { - .name = "G2ls", - .pvr = CPU_PPC_G2ls, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000006FFF2ULL, - }, - { /* Same as G2, with LE mode support */ - .name = "G2le", - .pvr = CPU_PPC_G2LE, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000007FFF3ULL, - }, - { - .name = "G2legp", - .pvr = CPU_PPC_G2LEgp, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000007FFF3ULL, - }, - { - .name = "G2lels", - .pvr = CPU_PPC_G2LEls, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_G2, - .flags = PPC_FLAGS_G2, - .msr_mask = 0x000000000007FFF3ULL, - }, -#endif - /* PowerPC 604 */ - { - .name = "604", - .pvr = CPU_PPC_604, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_604, - .flags = PPC_FLAGS_604, - .msr_mask = 0x000000000005FF77ULL, - }, - /* PowerPC 604e */ - { - .name = "604e", - .pvr = CPU_PPC_604E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_604, - .flags = PPC_FLAGS_604, - .msr_mask = 0x000000000005FF77ULL, - }, - /* PowerPC 604r */ - { - .name = "604r", - .pvr = CPU_PPC_604R, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_604, - .flags = PPC_FLAGS_604, - .msr_mask = 0x000000000005FF77ULL, - }, - /* generic G3 */ - { - .name = "G3", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* MPC740 (G3) */ - { - .name = "740", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - { - .name = "Arthur", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* 740E (G3) */ - { - .name = "740e", - .pvr = CPU_PPC_740E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* MPC740P (G3) */ - { - .name = "740p", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - { - .name = "Conan/Doyle", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, -#if defined (TODO) - /* MPC745 (G3) */ - { - .name = "745", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, - { - .name = "Goldfinger", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif -#if defined (TODO) - /* MPC745P (G3) */ - { - .name = "745p", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif - /* MPC750 (G3) */ - { - .name = "750", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* MPC750P (G3) */ - { - .name = "750p", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* 750E (G3) */ - { - .name = "750e", - .pvr = CPU_PPC_750E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750CXe (G3 embedded) */ - { - .name = "750cxe", - .pvr = CPU_PPC_750CXE, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750CXr (G3 embedded) */ - { - .name = "750cxr", - .pvr = CPU_PPC_750CXR, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750FX (G3 embedded) */ - { - .name = "750fx", - .pvr = CPU_PPC_750FX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750FL (G3 embedded) */ - { - .name = "750fl", - .pvr = CPU_PPC_750FL, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750GX (G3 embedded) */ - { - .name = "750gx", - .pvr = CPU_PPC_750GX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750L (G3 embedded) */ - { - .name = "750l", - .pvr = CPU_PPC_750L, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, - /* IBM 750CL (G3 embedded) */ - { - .name = "750cl", - .pvr = CPU_PPC_750CL, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x0, - .flags = PPC_FLAGS_7x0, - .msr_mask = 0x000000000007FF77ULL, - }, -#if defined (TODO) - /* MPC755 (G3) */ - { - .name = "755", - .pvr = CPU_PPC_755, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif -#if defined (TODO) - /* MPC755D (G3) */ - { - .name = "755d", - .pvr = CPU_PPC_755D, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif -#if defined (TODO) - /* MPC755E (G3) */ - { - .name = "755e", - .pvr = CPU_PPC_755E, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif -#if defined (TODO) - /* MPC755P (G3) */ - { - .name = "755p", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif -#if defined (TODO) - /* generic G4 */ - { - .name = "G4", - .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7400 (G4) */ - { - .name = "7400", - .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Max", - .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7410 (G4) */ - { - .name = "7410", - .pvr = CPU_PPC_7410, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Nitro", - .pvr = CPU_PPC_7410, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7441 (G4) */ - { - .name = "7441", - .pvr = CPU_PPC_7441, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7445 (G4) */ - { - .name = "7445", - .pvr = CPU_PPC_7445, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7447 (G4) */ - { - .name = "7447", - .pvr = CPU_PPC_7447, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7447A (G4) */ - { - .name = "7447A", - .pvr = CPU_PPC_7447A, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7448 (G4) */ - { - .name = "7448", - .pvr = CPU_PPC_7448, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7450 (G4) */ - { - .name = "7450", - .pvr = CPU_PPC_7450, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Vger", - .pvr = CPU_PPC_7450, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7450b (G4) */ - { - .name = "7450b", - .pvr = CPU_PPC_7450B, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7451 (G4) */ - { - .name = "7451", - .pvr = CPU_PPC_7451, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7451g (G4) */ - { - .name = "7451g", - .pvr = CPU_PPC_7451G, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7455 (G4) */ - { - .name = "7455", - .pvr = CPU_PPC_7455, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Apollo 6", - .pvr = CPU_PPC_7455, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7455F (G4) */ - { - .name = "7455f", - .pvr = CPU_PPC_7455F, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7455G (G4) */ - { - .name = "7455g", - .pvr = CPU_PPC_7455G, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7457 (G4) */ - { - .name = "7457", - .pvr = CPU_PPC_7457, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Apollo 7", - .pvr = CPU_PPC_7457, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7457A (G4) */ - { - .name = "7457A", - .pvr = CPU_PPC_7457A, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, - { - .name = "Apollo 7 PM", - .pvr = CPU_PPC_7457A, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 7457C (G4) */ - { - .name = "7457c", - .pvr = CPU_PPC_7457C, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_74xx, - .flags = PPC_FLAGS_74xx, - .msr_mask = 0x000000000205FF77ULL, - }, -#endif - /* 64 bits PowerPC */ -#if defined (TARGET_PPC64) -#if defined (TODO) - /* PowerPC 620 */ - { - .name = "620", - .pvr = CPU_PPC_620, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_620, - .flags = PPC_FLAGS_620, - .msr_mask = 0x800000000005FF73ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 630 (POWER3) */ - { - .name = "630", - .pvr = CPU_PPC_630, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_630, - .flags = PPC_FLAGS_630, - .msr_mask = xxx, - } - { - .name = "POWER3", - .pvr = CPU_PPC_630, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_630, - .flags = PPC_FLAGS_630, - .msr_mask = xxx, - } -#endif -#if defined (TODO) - /* PowerPC 631 (Power 3+)*/ - { - .name = "631", - .pvr = CPU_PPC_631, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_631, - .flags = PPC_FLAGS_631, - .msr_mask = xxx, - }, - { - .name = "POWER3+", - .pvr = CPU_PPC_631, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_631, - .flags = PPC_FLAGS_631, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* POWER4 */ - { - .name = "POWER4", - .pvr = CPU_PPC_POWER4, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER4, - .flags = PPC_FLAGS_POWER4, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* POWER4p */ - { - .name = "POWER4+", - .pvr = CPU_PPC_POWER4P, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER4, - .flags = PPC_FLAGS_POWER4, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* POWER5 */ - { - .name = "POWER5", - .pvr = CPU_PPC_POWER5, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER5, - .flags = PPC_FLAGS_POWER5, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* POWER5+ */ - { - .name = "POWER5+", - .pvr = CPU_PPC_POWER5P, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER5, - .flags = PPC_FLAGS_POWER5, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* POWER6 */ - { - .name = "POWER6", - .pvr = CPU_PPC_POWER6, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER6, - .flags = PPC_FLAGS_POWER6, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* PowerPC 970 */ - { - .name = "970", - .pvr = CPU_PPC_970, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_970, - .flags = PPC_FLAGS_970, - .msr_mask = 0x900000000204FF36ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 970FX (G5) */ - { - .name = "970fx", - .pvr = CPU_PPC_970FX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_970FX, - .flags = PPC_FLAGS_970FX, - .msr_mask = 0x800000000204FF36ULL, - }, -#endif -#if defined (TODO) - /* PowerPC 970MP */ - { - .name = "970MP", - .pvr = CPU_PPC_970MP, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_970, - .flags = PPC_FLAGS_970, - .msr_mask = 0x900000000204FF36ULL, - }, -#endif -#if defined (TODO) - /* PowerPC Cell */ - { - .name = "Cell", - .pvr = CPU_PPC_CELL, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_970, - .flags = PPC_FLAGS_970, - .msr_mask = 0x900000000204FF36ULL, - }, -#endif -#if defined (TODO) - /* RS64 (Apache/A35) */ - /* This one seems to support the whole POWER2 instruction set - * and the PowerPC 64 one. - */ - { - .name = "RS64", - .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "Apache", - .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "A35", - .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* RS64-II (NorthStar/A50) */ - { - .name = "RS64-II", - .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "NortStar", - .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "A50", - .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* RS64-III (Pulsar) */ - { - .name = "RS64-III", - .pvr = CPU_PPC_RS64III, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "Pulsar", - .pvr = CPU_PPC_RS64III, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, -#endif -#if defined (TODO) - /* RS64-IV (IceStar/IStar/SStar) */ - { - .name = "RS64-IV", - .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "IceStar", - .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "IStar", - .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, - { - .name = "SStar", - .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_RS64, - .flags = PPC_FLAGS_RS64, - .msr_mask = xxx, - }, -#endif - /* POWER */ -#if defined (TODO) - /* Original POWER */ - { - .name = "POWER", - .pvr = CPU_POWER, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER, - .flags = PPC_FLAGS_POWER, - .msr_mask = xxx, - }, -#endif -#endif /* defined (TARGET_PPC64) */ -#if defined (TODO) - /* POWER2 */ - { - .name = "POWER2", - .pvr = CPU_POWER2, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_POWER, - .flags = PPC_FLAGS_POWER, - .msr_mask = xxx, - }, -#endif - /* Generic PowerPCs */ -#if defined (TODO) - { - .name = "ppc64", - .pvr = CPU_PPC_970FX, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_PPC64, - .flags = PPC_FLAGS_PPC64, - .msr_mask = 0xA00000000204FF36ULL, - }, -#endif - { - .name = "ppc32", - .pvr = CPU_PPC_604, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_PPC32, - .flags = PPC_FLAGS_PPC32, - .msr_mask = 0x000000000005FF77ULL, - }, - /* Fallback */ - { - .name = "ppc", - .pvr = CPU_PPC_604, - .pvr_mask = 0xFFFFFFFF, - .insns_flags = PPC_INSNS_PPC32, - .flags = PPC_FLAGS_PPC32, - .msr_mask = 0x000000000005FF77ULL, - }, -}; - int ppc_find_by_name (const unsigned char *name, ppc_def_t **def) { int i, ret; @@ -4374,9 +5525,8 @@ void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) int i; for (i = 0; ; i++) { - (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n", - ppc_defs[i].name, - ppc_defs[i].pvr, ppc_defs[i].pvr_mask); + (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n", + ppc_defs[i].name, ppc_defs[i].pvr); if (strcmp(ppc_defs[i].name, "ppc") == 0) break; } |