diff options
| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2016-09-29 15:52:37 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-10-05 11:05:28 +1100 |
| commit | 2020b67d851affd9dd8b3732a5290d90be6187d1 (patch) | |
| tree | 7b02f122898aa26d0a1c870dcaa31f51c7351437 /target-ppc/translate/vmx-ops.inc.c | |
| parent | 7f516c9675285298826d4ef20ce1a093b13caf89 (diff) | |
target-ppc: fix vmx instruction type/type2
A few of the new instructions added inadvertently changed the type of
old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
declaration.
commit: b5d569a1 (target-ppc: add vector extract instructions)
commit: e7b1e06f (target-ppc: add vector insert instructions)
commit: 3aa56a19 (target-ppc: add vector compare not equal instructions)
New ISA 3.0 instructions added:
vextractub PPC_NONE PPC2_ISA300
vextractuh PPC_NONE PPC2_ISA300
vextractuw PPC_NONE PPC2_ISA300
vinsertb PPC_NONE PPC2_ISA300
vinserth PPC_NONE PPC2_ISA300
vinsertw PPC_NONE PPC2_ISA300
vcmpneb PPC_NONE PPC2_ISA300
vcmpneh PPC_NONE PPC2_ISA300
vcmpnew PPC_NONE PPC2_ISA300
Affected older instructions:
vspltb PPC_ALTIVEC PPC_NONE
vsplth PPC_ALTIVEC PPC_NONE
vspltw PPC_ALTIVEC PPC_NONE
vspltisb PPC_ALTIVEC PPC_NONE
vspltish PPC_ALTIVEC PPC_NONE
vspltisw PPC_ALTIVEC PPC_NONE
vcmpequb PPC_ALTIVEC PPC_NONE
vcmpequh PPC_ALTIVEC PPC_NONE
vcmpequw PPC_ALTIVEC PPC_NONE
Change the instruction type/type2 for the older instructions back to
what it was(PPC_ALTIVEC).
CC: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate/vmx-ops.inc.c')
| -rw-r--r-- | target-ppc/translate/vmx-ops.inc.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index b63e33dabb..ac1dc9b2b2 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -194,26 +194,26 @@ GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) GEN_VXRFORM(vcmpgefp, 3, 7) GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE) #define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \ GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \ PPC_NONE) GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000), GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000, - PPC2_ALTIVEC_207), + PPC_ALTIVEC), GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000), GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C), GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D), |