diff options
| author | Alexander Graf <agraf@suse.de> | 2015-11-11 22:49:39 +0000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2015-11-12 13:15:54 +1100 |
| commit | 4248b336d3c1b74e343842c5b478b165d75f5ce8 (patch) | |
| tree | 2192681ab9d32343ef07dd95f994263070b12352 /target-ppc/translate.c | |
| parent | 31e49ac192f782d594bbd04070fe79e800b7813f (diff) | |
PPC: Allow Rc bit to be set on mtspr
According to the ISA setting the Rc bit on mtspr is undefined behavior.
Real 750 hardware simply ignores the bit and doesn't touch cr0 though.
Unfortunately, Mac OS 9 relies on this fact and executes a few mtspr
instructions (to set XER for example) with Rc set.
So let's handle the bit the same way hardware does and ignore it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 308ad68880..41a7258486 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9884,7 +9884,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), -GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), +GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |