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| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-12 23:29:14 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-12 23:29:14 +0000 |
| commit | 65d6c0f33c1a496d2a782bb0ef2ef18d4ed6b763 (patch) | |
| tree | 963351c4967cadac20f88ba9654a2c5c116e0a74 /target-ppc/translate.c | |
| parent | 4f6cf9e839313f2da5a6690363fbe1756c20c2ca (diff) | |
PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d1741b6a3b..8663eabb48 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -5822,7 +5822,7 @@ GEN_VR_STX(vxl, 0x07, 0x0F); /*** SPE extension ***/ /* Register moves */ -#if TARGET_GPR_BITS < 64 +#if !defined(TARGET_PPC64) GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr); GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr); @@ -5836,7 +5836,7 @@ GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr); GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr); #endif -#else /* TARGET_GPR_BITS < 64 */ +#else /* !defined(TARGET_PPC64) */ /* No specific load/store functions: GPRs are already 64 bits */ #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0 @@ -5851,7 +5851,7 @@ GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr); #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr #endif -#endif /* TARGET_GPR_BITS < 64 */ +#endif /* !defined(TARGET_PPC64) */ #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ |