diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-01 05:16:57 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-01 05:16:57 +0000 |
| commit | 7dbe11acd807b7a1566b2fe665333a49f8358de0 (patch) | |
| tree | b0c9681451bcb1d5631c564e8a5d6b9bd56bb725 /target-ppc/op_helper.c | |
| parent | 578bb25230229307c0b6ff62ae03ac0fbda27b18 (diff) | |
Handle all MMU models in switches, even if it's just to abort because of lack
of supporting code.
Implement 74xx software TLB model.
Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss
on those processors.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/op_helper.c')
| -rw-r--r-- | target-ppc/op_helper.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index a7c81776fd..8bb93ed36b 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -2363,6 +2363,27 @@ void do_load_6xx_tlb (int is_code) way, is_code, CMP, RPN); } +void do_load_74xx_tlb (int is_code) +{ + target_ulong RPN, CMP, EPN; + int way; + + RPN = env->spr[SPR_PTELO]; + CMP = env->spr[SPR_PTEHI]; + EPN = env->spr[SPR_TLBMISS] & ~0x3; + way = env->spr[SPR_TLBMISS] & 0x3; +#if defined (DEBUG_SOFTWARE_TLB) + if (loglevel != 0) { + fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n", + __func__, (unsigned long)T0, (unsigned long)EPN, + (unsigned long)CMP, (unsigned long)RPN, way); + } +#endif + /* Store this TLB */ + ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK), + way, is_code, CMP, RPN); +} + static target_ulong booke_tlb_to_page_size (int size) { return 1024 << (2 * size); |