As icbi is not a priviledge instruction and is treated as a load by the MMU

it needs to be implemented for every MMU translation mode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2492 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 0 insertions, 29 deletions

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 7bc59332df..7ef06b20b0 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -808,35 +808,6 @@ void do_td (int flags)
 }
 #endif
 
-/* Instruction cache invalidation helper */
-void do_icbi (void)
-{
-    uint32_t tmp;
-    /* Invalidate one cache line :
-     * PowerPC specification says this is to be treated like a load
-     * (not a fetch) by the MMU. To be sure it will be so,
-     * do the load "by hand".
-     */
-    tmp = ldl_kernel((uint32_t)T0);
-    T0 &= ~(ICACHE_LINE_SIZE - 1);
-    tb_invalidate_page_range((uint32_t)T0, (uint32_t)(T0 + ICACHE_LINE_SIZE));
-}
-
-#if defined(TARGET_PPC64)
-void do_icbi_64 (void)
-{
-    uint64_t tmp;
-    /* Invalidate one cache line :
-     * PowerPC specification says this is to be treated like a load
-     * (not a fetch) by the MMU. To be sure it will be so,
-     * do the load "by hand".
-     */
-    tmp = ldq_kernel((uint64_t)T0);
-    T0 &= ~(ICACHE_LINE_SIZE - 1);
-    tb_invalidate_page_range((uint64_t)T0, (uint64_t)(T0 + ICACHE_LINE_SIZE));
-}
-#endif
-
 /*****************************************************************************/
 /* PowerPC 601 specific instructions (POWER bridge) */
 void do_POWER_abso (void)