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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:54:59 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:54:59 +0000
commit6ce0ca1204c0536d071f86ac1309c5b6fd99c351 (patch)
tree3c6017c308f8a83f77f116c5a96d697336ba4100 /target-ppc/helper.c
parent4e98d8cf0a7672bb1208e534112f00d7019998a8 (diff)
Enable 64bit mode on interrupts
Real 970s enable MSR_SF on all interrupts. The current code didn't do this until now, so let's activate it! Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/helper.c')
-rw-r--r--target-ppc/helper.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 5f3199ea3a..60a63b8e73 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2612,7 +2612,7 @@ static always_inline void powerpc_excp (CPUState *env,
new_msr |= (target_ulong)1 << MSR_CM;
}
} else {
- if (!msr_isf) {
+ if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
new_msr &= ~((target_ulong)1 << MSR_SF);
vector = (uint32_t)vector;
} else {
@@ -2793,6 +2793,10 @@ void cpu_ppc_reset (void *opaque)
ppc_tlb_invalidate_all(env);
#endif
env->msr = msr & env->msr_mask;
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64)
+ env->msr |= (1ULL << MSR_SF);
+#endif
hreg_compute_hflags(env);
env->reserve = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */