diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-01-15 08:10:35 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:35 +0100 |
| commit | b24d0b472b0d471e93ccc7fc7d4fd6ed30e7e434 (patch) | |
| tree | cd1a2bbc045d42502a17f38bcd610e0f8bdbf00c /target-ppc/fpu_helper.c | |
| parent | ab9408a2d11670d15b2692ca60646d8da8158d6f (diff) | |
target-ppc: VSX Stage 4: Add xsdivsp
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/fpu_helper.c')
| -rw-r--r-- | target-ppc/fpu_helper.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index dc9849f209..49cf09a53f 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1874,7 +1874,7 @@ VSX_MUL(xvmulsp, 4, float32, f32, 0, 0) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_DIV(op, nels, tp, fld, sfprf) \ +#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xa, xb; \ @@ -1903,6 +1903,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -1912,9 +1916,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_DIV(xsdivdp, 1, float64, f64, 1) -VSX_DIV(xvdivdp, 2, float64, f64, 0) -VSX_DIV(xvdivsp, 4, float32, f32, 0) +VSX_DIV(xsdivdp, 1, float64, f64, 1, 0) +VSX_DIV(xsdivsp, 1, float64, f64, 1, 1) +VSX_DIV(xvdivdp, 2, float64, f64, 0, 0) +VSX_DIV(xvdivsp, 4, float32, f32, 0, 0) /* VSX_RE - VSX floating point reciprocal estimate * op - instruction mnemonic |