diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-04-20 08:56:22 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:43 +0200 |
| commit | 7d08d85645def18eac2a9d672c1868a35e0bcf79 (patch) | |
| tree | bb70d80e36ac6fe6878dc29bff4ee9376f70ffa9 /target-ppc/fpu_helper.c | |
| parent | 44bc0c4d3e90bfa1fafdbcc19d023d2d4b119eed (diff) | |
target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with
up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit
marked as invalid anymore. Instead this is checked in the helper, which
therefore needs to access to the insns/insns_flags2. They are added in
the DisasContext struct. Finally change all accesses to the opcode fields
through extract helpers, prefixed with FP for consistency.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/fpu_helper.c')
| -rw-r--r-- | target-ppc/fpu_helper.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 1f0eeab484..4f6021835f 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -430,20 +430,17 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { - /* - * We use only the 32 LSB of the incoming fpr - */ - uint32_t prev, new; + target_ulong prev, new; int i; prev = env->fpscr; - new = (uint32_t)arg; - new &= ~0x60000000; - new |= prev & 0x60000000; - for (i = 0; i < 8; i++) { + new = (target_ulong)arg; + new &= ~0x60000000LL; + new |= prev & 0x60000000LL; + for (i = 0; i < sizeof(target_ulong) * 2; i++) { if (mask & (1 << i)) { - env->fpscr &= ~(0xF << (4 * i)); - env->fpscr |= new & (0xF << (4 * i)); + env->fpscr &= ~(0xFLL << (4 * i)); + env->fpscr |= new & (0xFLL << (4 * i)); } } /* Update VX and FEX */ |