diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-24 02:03:55 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-24 02:03:55 +0000 |
| commit | 6b542af760f44409b40441225fbef31a3b4bdbe1 (patch) | |
| tree | d7371ec9d77673e4d2cb59a249750fe0cc0d0529 /target-ppc/exec.h | |
| parent | 69facb7897ef6404175b4739751f9255fc0c8a2e (diff) | |
Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/exec.h')
| -rw-r--r-- | target-ppc/exec.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h index beaa39ab04..76fdb0b1d6 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -37,10 +37,12 @@ register struct CPUPPCState *env asm(AREG0); #define T0 (env->t0) #define T1 (env->t1) #define T2 (env->t2) +#define TDX "%016" PRIx64 #else register unsigned long T0 asm(AREG1); register unsigned long T1 asm(AREG2); register unsigned long T2 asm(AREG3); +#define TDX "%016lx" #endif /* We may, sometime, need 64 bits registers on 32 bits targets */ #if (HOST_LONG_BITS == 32) |