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| author | Tom Musta <tommusta@gmail.com> | 2014-06-16 11:03:19 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-27 13:48:21 +0200 |
| commit | 623e250abdca2c29830793e3ac81a9e405f33216 (patch) | |
| tree | 953162c9135dc0c65c72543e961ef880f50f63d8 /target-ppc/cpu.h | |
| parent | ff4873cb8c81db89668d8b56e19e57b852edb5f5 (diff) | |
linux-user: Correct AUXV Cache Line Sizes for PowerPC
Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the
CPU model's cache line sizes. This fixes memory clobbering problems on more
recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction
when N is sufficiently large and many of the newer server CPUs have cache lines
sizes of 128 bytes.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
0 files changed, 0 insertions, 0 deletions