diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-09-17 14:25:46 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:36:27 +1100 |
| commit | 959082fc4a93a016a6b697e1e0c2b373d8a3a373 (patch) | |
| tree | dda759b30da56f02813c9328372a4af3b23c0cb0 /target-mips | |
| parent | 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 (diff) | |
target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index aa0e0fd55e..66147d887f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19619,8 +19619,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(ctx.pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -19659,8 +19660,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, } ctx.pc += insn_bytes; - num_insns++; - /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the |