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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-08-29 23:07:39 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-09-06 11:09:39 +0200 |
| commit | 9e56e7562485c3f6f84c40cdee558168ea193a25 (patch) | |
| tree | 15a14ee3346c89e4190685d4ce70b0980a951065 /target-mips/translate.c | |
| parent | 1dab005ae2ff3f9b83e02f25aa77c5e262404505 (diff) | |
mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs and
TCs start in sleep.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 1bd1d62705..d5b1c765fb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12813,6 +12813,32 @@ void cpu_reset (CPUMIPSState *env) /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); env->hflags = MIPS_HFLAG_CP0; + + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + int i; + + /* Only TC0 on VPE 0 starts as active. */ + for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { + env->tcs[i].CP0_TCBind = env->cpu_index << CP0TCBd_CurVPE; + env->tcs[i].CP0_TCHalt = 1; + } + env->active_tc.CP0_TCHalt = 1; + env->halted = 1; + + if (!env->cpu_index) { + /* VPE0 starts up enabled. */ + env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + + /* TC0 starts up unhalted. */ + env->halted = 0; + env->active_tc.CP0_TCHalt = 0; + env->tcs[0].CP0_TCHalt = 0; + /* With thread 0 active. */ + env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); + env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); + } + } #endif #if defined(TARGET_MIPS64) if (env->cpu_model->insn_flags & ISA_MIPS3) { |