diff options
author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 18:05:37 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 18:05:37 +0000 |
commit | d26bc2118e99702eb8c1bb240786bcadd7fa21ac (patch) | |
tree | 2d3523234b61325aff6bf5eb857a67a5fddaeb97 /target-mips/translate.c | |
parent | 5850586c072456e6f007096ea8a489c97118f8f1 (diff) |
Clean out the N32 macros from target-mips, and introduce MIPS ABI specific
defines for linux-user.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r-- | target-mips/translate.c | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 9ec28eaccc..578cd9a25c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -590,7 +590,7 @@ do { \ } \ } while (0) -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) #define GEN_LOAD_IMM_TN(Tn, Imm) \ do { \ if (Imm == 0) { \ @@ -638,7 +638,7 @@ do { \ static always_inline void gen_save_pc(target_ulong pc) { -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) if (pc == (int32_t)pc) { gen_op_save_pc(pc); } else { @@ -651,7 +651,7 @@ static always_inline void gen_save_pc(target_ulong pc) static always_inline void gen_save_btarget(target_ulong btarget) { -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) if (btarget == (int32_t)btarget) { gen_op_save_btarget(btarget); } else { @@ -802,7 +802,7 @@ static GenOpFunc *gen_op_s##width[] = { \ } #endif -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) OP_LD_TABLE(d); OP_LD_TABLE(dl); OP_LD_TABLE(dr); @@ -852,7 +852,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) { -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_LWU: op_ldst(lwu); GEN_STORE_TN_REG(rt, T0); @@ -1048,7 +1048,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_ADDI: case OPC_ADDIU: -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DADDI: case OPC_DADDIU: #endif @@ -1068,7 +1068,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, case OPC_SLL: case OPC_SRA: case OPC_SRL: -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DSLL: case OPC_DSRA: case OPC_DSRL: @@ -1091,7 +1091,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, gen_op_add(); opn = "addiu"; break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DADDI: save_cpu_state(ctx, 1); gen_op_daddo(); @@ -1155,7 +1155,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, break; } break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DSLL: gen_op_dsll(); opn = "dsll"; @@ -1260,7 +1260,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, gen_op_sub(); opn = "subu"; break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DADD: save_cpu_state(ctx, 1); gen_op_daddo(); @@ -1346,7 +1346,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, break; } break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DSLLV: gen_op_dsllv(); opn = "dsllv"; @@ -1451,7 +1451,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, gen_op_multu(); opn = "multu"; break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DDIV: gen_op_ddiv(); opn = "ddiv"; @@ -1512,7 +1512,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, gen_op_clz(); opn = "clz"; break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DCLO: gen_op_dclo(); opn = "dclo"; @@ -2319,7 +2319,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) check_insn(env, ctx, ISA_MIPS3); gen_op_mfc0_xcontext(); rn = "XContext"; @@ -2901,7 +2901,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) check_insn(env, ctx, ISA_MIPS3); gen_op_mtc0_xcontext(); rn = "XContext"; @@ -3111,7 +3111,7 @@ die: generate_exception(ctx, EXCP_RI); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; @@ -4254,7 +4254,7 @@ die: #endif generate_exception(ctx, EXCP_RI); } -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ +#endif /* TARGET_MIPS64 */ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int u, int sel, int h) @@ -4604,7 +4604,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int gen_mtc0(env, ctx, rd, ctx->opcode & 0x7); opn = "mtc0"; break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DMFC0: check_insn(env, ctx, ISA_MIPS3); if (rt == 0) { @@ -5877,7 +5877,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, /* MIPS16 extension to MIPS32 */ /* SmartMIPS extension to MIPS32 */ -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) /* MDMX extension to MIPS64 */ @@ -5987,7 +5987,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) /* MIPS64 specific opcodes */ case OPC_DSLL: case OPC_DSRL ... OPC_DSRA: @@ -6043,7 +6043,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } /* Treat as NOP. */ break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DCLZ ... OPC_DCLO: check_insn(env, ctx, ISA_MIPS64); check_mips_64(ctx); @@ -6130,7 +6130,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) gen_op_yield(); GEN_STORE_TN_REG(rd, T0); break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: check_insn(env, ctx, ISA_MIPS64R2); @@ -6192,7 +6192,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) case OPC_MTC0: case OPC_MFTR: case OPC_MTTR: -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DMFC0: case OPC_DMTC0: #endif @@ -6313,7 +6313,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) case OPC_CTC1: gen_cp1(ctx, op1, rt, rd); break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) case OPC_DMFC1: case OPC_DMTC1: check_insn(env, ctx, ISA_MIPS3); @@ -6398,7 +6398,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) /* MIPS64 opcodes */ case OPC_LWU: case OPC_LDL ... OPC_LDR: @@ -6665,7 +6665,7 @@ void dump_fpu (CPUState *env) } } -#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) /* Debug help: The architecture requires 32bit code to maintain proper sign-extened values on 64bit machines. */ @@ -6720,7 +6720,7 @@ void cpu_dump_state (CPUState *env, FILE *f, env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); if (env->hflags & MIPS_HFLAG_FPU) fpu_dump_state(env, f, cpu_fprintf, flags); -#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); #endif } |