diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-04 19:13:47 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-04 19:13:47 +0000 |
| commit | e00fcff7106acaa0062b155524fd62684b0e0193 (patch) | |
| tree | b76577492f257d9c464c7d4c45a92d5666e11492 /target-mips/translate.c | |
| parent | ea0f49a74dc18b063c7fd5076dcfa3a402c48e92 (diff) | |
target-mips: use the new rotr/rotri instructions
Acked-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5622 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 48 |
1 files changed, 5 insertions, 43 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index ec375e1201..4b0339ea3c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1455,17 +1455,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, if (env->insn_flags & ISA_MIPS32R2) { if (uimm != 0) { TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); tcg_gen_trunc_tl_i32(r_tmp1, t0); - tcg_gen_movi_i32(r_tmp2, 0x20); - tcg_gen_subi_i32(r_tmp2, r_tmp2, uimm); - tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2); - tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm); - tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2); + tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm); tcg_gen_ext_i32_tl(t0, r_tmp1); tcg_temp_free(r_tmp1); - tcg_temp_free(r_tmp2); } opn = "rotr"; } else { @@ -1500,14 +1494,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, /* drotr is decoded as dsrl on non-R2 CPUs */ if (env->insn_flags & ISA_MIPS32R2) { if (uimm != 0) { - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); - - tcg_gen_movi_tl(r_tmp1, 0x40); - tcg_gen_subi_tl(r_tmp1, r_tmp1, uimm); - tcg_gen_shl_tl(r_tmp1, t0, r_tmp1); - tcg_gen_shri_tl(t0, t0, uimm); - tcg_gen_or_tl(t0, t0, r_tmp1); - tcg_temp_free(r_tmp1); + tcg_gen_rotri_tl(t0, t0, uimm); } opn = "drotr"; } else { @@ -1538,18 +1525,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ if (env->insn_flags & ISA_MIPS32R2) { - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL); - - tcg_gen_movi_tl(r_tmp1, 0x40); - tcg_gen_movi_tl(r_tmp2, 32); - tcg_gen_addi_tl(r_tmp2, r_tmp2, uimm); - tcg_gen_sub_tl(r_tmp1, r_tmp1, r_tmp2); - tcg_gen_shl_tl(r_tmp1, t0, r_tmp1); - tcg_gen_shr_tl(t0, t0, r_tmp2); - tcg_gen_or_tl(t0, t0, r_tmp1); - tcg_temp_free(r_tmp1); - tcg_temp_free(r_tmp2); + tcg_gen_rotri_tl(t0, t0, uimm + 32); opn = "drotr32"; } else { tcg_gen_shri_tl(t0, t0, uimm + 32); @@ -1809,19 +1785,12 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, { TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); - TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32); tcg_gen_trunc_tl_i32(r_tmp1, t0); tcg_gen_trunc_tl_i32(r_tmp2, t1); - tcg_gen_movi_i32(r_tmp3, 0x20); - tcg_gen_sub_i32(r_tmp3, r_tmp3, r_tmp1); - tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3); - tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1); - tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3); - tcg_gen_ext_i32_tl(t0, r_tmp1); + tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp1); tcg_temp_free(r_tmp2); - tcg_temp_free(r_tmp3); tcg_gen_br(l2); } gen_set_label(l1); @@ -1869,14 +1838,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); { - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); - - tcg_gen_movi_tl(r_tmp1, 0x40); - tcg_gen_sub_tl(r_tmp1, r_tmp1, t0); - tcg_gen_shl_tl(r_tmp1, t1, r_tmp1); - tcg_gen_shr_tl(t0, t1, t0); - tcg_gen_or_tl(t0, t0, r_tmp1); - tcg_temp_free(r_tmp1); + tcg_gen_rotr_tl(t0, t1, t0); tcg_gen_br(l2); } gen_set_label(l1); |