diff options
| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-10-23 13:58:08 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-10-24 22:32:56 +0200 |
| commit | 536446e914caa8702053efb506b4f4d92128d7e6 (patch) | |
| tree | f46327a8408d5923dcc6000f3bdbcd5d65dd8a16 /target-microblaze | |
| parent | 09b9f113ad9e2bad57b41f6c67228353972ad1af (diff) | |
microblaze: Move the saving of the reservation addr into gen_load
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-microblaze')
| -rw-r--r-- | target-microblaze/translate.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 232015aa9c..021a504ec0 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -863,7 +863,7 @@ static void dec_imm(DisasContext *dc) } static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, - unsigned int size) + unsigned int size, bool exclusive) { int mem_index = cpu_mmu_index(dc->env); @@ -875,6 +875,10 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, tcg_gen_qemu_ld32u(dst, addr, mem_index); } else cpu_abort(dc->env, "Incorrect load size %d\n", size); + + if (exclusive) { + tcg_gen_st_tl(addr, cpu_env, offsetof(CPUMBState, res_addr)); + } } static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) @@ -1046,7 +1050,7 @@ static void dec_load(DisasContext *dc) * into v. If the load succeeds, we verify alignment of the * address and if that succeeds we write into the destination reg. */ - gen_load(dc, v, *addr, size); + gen_load(dc, v, *addr, size, ex); tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), @@ -1061,20 +1065,19 @@ static void dec_load(DisasContext *dc) tcg_temp_free(v); } else { if (dc->rd) { - gen_load(dc, cpu_R[dc->rd], *addr, size); + gen_load(dc, cpu_R[dc->rd], *addr, size, ex); if (rev) { dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size); } } else { /* We are loading into r0, no need to reverse. */ - gen_load(dc, env_imm, *addr, size); + gen_load(dc, env_imm, *addr, size, ex); } } if (ex) { /* lwx */ /* no support for for AXI exclusive so always clear C */ write_carryi(dc, 0); - tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr)); } if (addr == &t) |