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authorPeter Maydell <peter.maydell@linaro.org>2016-01-21 15:53:25 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-01-21 15:53:25 +0000
commit83446463dd7b7e3d7e69bcaa079d6a5d8cd3cd76 (patch)
tree9989294bc7ad481c06d57b38dc103d810140ef29 /target-i386/cpu.c
parent1a4f446f81c63151efc30f3ce60a749e8a4cf680 (diff)
parentf74eefe0b98cd7e13825de8e8d9f32e22aed102c (diff)
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
X86 queue, 2016-01-21 # gpg: Signature made Thu 21 Jan 2016 15:08:40 GMT using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: target-i386: Add PKU and and OSPKE support target-i386: Add support to migrate vcpu's TSC rate target-i386: Reorganize TSC rate setting code target-i386: Fallback vcpu's TSC rate to value returned by KVM target-i386: Add suffixes to MMReg struct fields target-i386: Define MMREG_UNION macro target-i386: Define MMXReg._d field target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* target-i386: Rename struct XMMReg to ZMMReg target-i386: Use a _q array on MMXReg too target-i386/ops_sse.h: Use MMX_Q macro target-i386: Rename optimize_flags_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-i386/cpu.c')
-rw-r--r--target-i386/cpu.c27
1 files changed, 24 insertions, 3 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4430494085..b2556441cc 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -263,6 +263,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
"clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
};
+static const char *cpuid_7_0_ecx_feature_name[] = {
+ NULL, NULL, NULL, "pku",
+ "ospke", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+};
+
static const char *cpuid_apm_edx_feature_name[] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -352,6 +363,7 @@ static const char *cpuid_6_feature_name[] = {
CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
CPUID_7_0_EBX_RDSEED */
+#define TCG_7_0_ECX_FEATURES 0
#define TCG_APM_FEATURES 0
#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
@@ -409,6 +421,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.cpuid_reg = R_EBX,
.tcg_features = TCG_7_0_EBX_FEATURES,
},
+ [FEAT_7_0_ECX] = {
+ .feat_names = cpuid_7_0_ecx_feature_name,
+ .cpuid_eax = 7,
+ .cpuid_needs_ecx = true, .cpuid_ecx = 0,
+ .cpuid_reg = R_ECX,
+ .tcg_features = TCG_7_0_ECX_FEATURES,
+ },
[FEAT_8000_0007_EDX] = {
.feat_names = cpuid_apm_edx_feature_name,
.cpuid_eax = 0x80000007,
@@ -469,6 +488,8 @@ static const ExtSaveArea ext_save_areas[] = {
.offset = 0x480, .size = 0x200 },
[7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = 0x680, .size = 0x400 },
+ [9] = { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
+ .offset = 0xA80, .size = 0x8 },
};
const char *get_register_name_32(unsigned int reg)
@@ -1728,7 +1749,7 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
return;
}
- cpu->env.tsc_khz = value / 1000;
+ cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
}
static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
@@ -2390,7 +2411,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
if (count == 0) {
*eax = 0; /* Maximum ECX value for sub-leaves */
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
- *ecx = 0; /* Reserved */
+ *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
*edx = 0; /* Reserved */
} else {
*eax = 0;
@@ -3091,7 +3112,7 @@ static void x86_cpu_initfn(Object *obj)
/* init various static tables used in TCG mode */
if (tcg_enabled() && !inited) {
inited = 1;
- optimize_flags_init();
+ tcg_x86_init();
}
}