diff options
| author | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-13 10:59:14 +0000 |
|---|---|---|
| committer | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-13 10:59:14 +0000 |
| commit | cf1d97f07480b6197aebc489938b4e1fed78d3e7 (patch) | |
| tree | d4ae1d25078f714690f5b01761f2bffd5d57f115 /target-cris/helper.c | |
| parent | 3bd8c5e4f1fdb61a3eb8a4a8b6e5b4cf1156ba76 (diff) | |
CRIS: Improve TLB management and handle delayslots at page boundaries.
* Dont flush the entire qemu tlb when the $pid changes. Instead we go through
the guests TLB and choose entries that need to be flushed.
* Add env->dslot and handle delayslots at pageboundaries.
* Remove some unused code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/helper.c')
| -rw-r--r-- | target-cris/helper.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c index f537361c96..5548b76073 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -97,9 +97,10 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); } if (r > 0) - D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x ismmu=%d vec=%x\n", - __func__, r, env->interrupt_request, - address, is_softmmu, res.bf_vec)); + D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x" + " phy=%x ismmu=%d vec=%x pc=%x\n", + __func__, r, env->interrupt_request, + address, res.phy, is_softmmu, res.bf_vec, env->pc)); return r; } @@ -138,13 +139,19 @@ void do_interrupt(CPUState *env) break; } - if ((env->pregs[PR_CCS] & U_FLAG)) { - D(fprintf(logfile, "excp isr=%x PC=%x SP=%x ERP=%x pid=%x ccs=%x cc=%d %x\n", - ex_vec, env->pc, + if (env->dslot) { + D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x" + " ERP=%x pid=%x ccs=%x cc=%d %x\n", + ex_vec, env->pc, env->dslot, env->regs[R_SP], env->pregs[PR_ERP], env->pregs[PR_PID], env->pregs[PR_CCS], env->cc_op, env->cc_mask)); + /* We loose the btarget, btaken state here so rexec the + branch. */ + env->pregs[PR_ERP] -= env->dslot; + /* Exception starts with dslot cleared. */ + env->dslot = 0; } env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |