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authorDaniel P. Berrange <berrange@redhat.com>2015-08-26 12:17:13 +0100
committerMichael Tokarev <mjt@tls.msk.ru>2015-09-11 10:21:38 +0300
commitb6af097528caba5b23b79db3f1f1fd08fa4fa11e (patch)
tree4989d369c9cdcfb6854219d33517ff23e616ab6b /target-arm
parenta8f15a27752d855d339befd8de4f0ad1c4dbb0ab (diff)
maint: remove / fix many doubled words
Many source files have doubled words (eg "the the", "to to", and so on). Most of these can simply be removed, but a couple were actual mis-spellings (eg "to to" instead of "to do"). There was even one triple word score "to to to" :-) Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/cpu.h4
-rw-r--r--target-arm/helper.c2
-rw-r--r--target-arm/translate.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4bd5dc875c..36407de6b3 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -173,7 +173,7 @@ typedef struct CPUARMState {
uint32_t GE; /* cpsr[19:16] */
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
- uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
+ uint64_t daif; /* exception masks, in the bits they are in PSTATE */
uint64_t elr_el[4]; /* AArch64 exception link regs */
uint64_t sp_el[4]; /* AArch64 banked stack pointers */
@@ -1488,7 +1488,7 @@ bool write_list_to_cpustate(ARMCPU *cpu);
*/
bool write_cpustate_to_list(ARMCPU *cpu);
-/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
+/* Does the core conform to the "MicroController" profile. e.g. Cortex-M3.
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
conventional cores (ie. Application or Realtime profile). */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fc4b65fd54..d453120874 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2123,7 +2123,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
- /* Update the masks corresponding to the the TCR bank being written
+ /* Update the masks corresponding to the TCR bank being written
* Note that we always calculate mask and base_mask, but
* they are only used for short-descriptor tables (ie if EAE is 0);
* for long-descriptor tables the TCR fields are used differently
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0bd3d0517b..ae705775d1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8500,7 +8500,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
/* Perform base writeback before the loaded value to
ensure correct behavior with overlapping index registers.
- ldrd with base writeback is is undefined if the
+ ldrd with base writeback is undefined if the
destination and index registers overlap. */
if (!(insn & (1 << 24))) {
gen_add_datah_offset(s, insn, address_offset, addr);