diff options
| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-02-07 03:34:35 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-02-07 03:34:35 +0000 |
| commit | 3aa22b4b53d4a8f5ae6b073c7c267b6ec9aabf63 (patch) | |
| tree | cb254b31e4baa1a7f07bd0586e30af9e5feb1a84 /target-arm | |
| parent | af2f67333f0b45b3f95103f580752f3f0514cf8f (diff) | |
Fix Thumb variable shift condition code bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1748 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index d5cbc5ee1d..77c8957af8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -1930,12 +1930,15 @@ static void disas_thumb_insn(DisasContext *s) break; case 0x2: /* lsl */ gen_op_shll_T1_T0_cc(); + gen_op_logic_T1_cc(); break; case 0x3: /* lsr */ gen_op_shrl_T1_T0_cc(); + gen_op_logic_T1_cc(); break; case 0x4: /* asr */ gen_op_sarl_T1_T0_cc(); + gen_op_logic_T1_cc(); break; case 0x5: /* adc */ gen_op_adcl_T0_T1_cc(); @@ -1945,6 +1948,7 @@ static void disas_thumb_insn(DisasContext *s) break; case 0x7: /* ror */ gen_op_rorl_T1_T0_cc(); + gen_op_logic_T1_cc(); break; case 0x8: /* tst */ gen_op_andl_T0_T1(); |