diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2015-10-26 14:01:55 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-27 15:59:46 +0000 |
| commit | 5c31a10d16c595d6a59e3e7fc1808c3b1d03e02f (patch) | |
| tree | 15bb4eb132b24e6722c948dac582903ecc749b20 /target-arm | |
| parent | 59e055307392fdf99b86c8cbcd33a7e261dcbdb1 (diff) | |
target-arm: lpae: Make t0sz and t1sz signed integers
Make t0sz and t1sz signed integers to match tsz and to make
it easier to implement support for AArch32 negative t0sz.
t1sz is changed for consistensy.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1445864527-14520-3-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 7e3558593a..d07b4b7cf3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6535,12 +6535,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6); + int32_t t0sz = extract32(tcr->raw_tcr, 0, 6); if (va_size == 64) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } - uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6); + int32_t t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16); |