diff options
| author | Alexander Graf <agraf@suse.de> | 2013-12-17 19:42:32 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:32 +0000 |
| commit | 11e169de9940b9dc057e534ecf864c542fafb425 (patch) | |
| tree | a68671f0f2fcd2f24e7f10077144522860d02be3 /target-arm/translate.h | |
| parent | 87462e0f41fccc353f9c902caed563ab7cbdd8ed (diff) | |
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: renamed functions, adapted to new decoder layout]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-arm/translate.h')
| -rw-r--r-- | target-arm/translate.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index 878918176f..23a45daff8 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -24,6 +24,9 @@ typedef struct DisasContext { int vec_len; int vec_stride; int aarch64; +#define TMP_A64_MAX 16 + int tmp_a64_count; + TCGv_i64 tmp_a64[TMP_A64_MAX]; } DisasContext; extern TCGv_ptr cpu_env; |