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| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-18 15:53:28 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-18 15:53:28 +0200 |
| commit | 98a463171b9a73cd178c6986a83742cbe18375a4 (patch) | |
| tree | eaedc165dbaed4193be4d0dc95d6aca373e8e394 /target-arm/translate.c | |
| parent | b567b38c2c1d8096e1eb0bc306470d0888f52eff (diff) | |
target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 368278bcc8..d1e1d30248 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6337,7 +6337,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) else ARCH(6); addr = tcg_temp_local_new_i32(); - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); if (insn & (1 << 20)) { gen_helper_mark_exclusive(cpu_env, addr); switch (op1) { @@ -7133,7 +7133,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) } else if ((insn & (1 << 23)) == 0) { /* Load/store exclusive word. */ addr = tcg_temp_local_new(); - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); if (insn & (1 << 20)) { gen_helper_mark_exclusive(cpu_env, addr); tmp = gen_ld32(addr, IS_USER(s)); @@ -7180,7 +7180,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) so it is good enough. */ op = (insn >> 4) & 0x3; addr = tcg_temp_local_new(); - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); if (insn & (1 << 20)) { gen_helper_mark_exclusive(cpu_env, addr); switch (op) { |