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authorPeter Maydell <peter.maydell@linaro.org>2016-02-23 15:36:43 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-26 15:09:41 +0000
commit235ea1f5c89abf30e452539b973b0dbe43d3fe2b (patch)
tree926cd2da5ac6f850018a29d2a2a5226ed19e1e95 /target-arm/helper.h
parent4d1e324b2241017c92d816ec3af51a14685dbf62 (diff)
target-arm: Give CPSR setting on 32-bit exception return its own helper
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.h')
-rw-r--r--target-arm/helper.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/helper.h b/target-arm/helper.h
index c98e9cea3d..ea13202b17 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -57,6 +57,7 @@ DEF_HELPER_2(pre_smc, void, env, i32)
DEF_HELPER_1(check_breakpoints, void, env)
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
+DEF_HELPER_2(cpsr_write_eret, void, env, i32)
DEF_HELPER_1(cpsr_read, i32, env)
DEF_HELPER_3(v7m_msr, void, env, i32, i32)