diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-10-24 16:26:56 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-24 16:26:56 +0100 |
| commit | 19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e (patch) | |
| tree | be8919d03be424ede566db09efe884a98fa13c30 /target-arm/helper.c | |
| parent | caae8032d3bd0a54f09abdae7624f52dece5ffd6 (diff) | |
target-arm: Implement new HLT trap for semihosting
Version 2.0 of the semihosting specification introduces new trap
instructions for AArch32: HLT 0xF000 for A32 and HLT 0x3C for T32.
Implement these (in the same way we implement the existing HLT
semihosting trap for A64).
The old traps via SVC and BKPT are unaffected.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1476792973-18508-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index cb83ee2008..25b15dc100 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6573,12 +6573,19 @@ static inline bool check_for_semihosting(CPUState *cs) /* Only intercept calls from privileged modes, to provide some * semblance of security. */ - if (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) { + if (cs->exception_index != EXCP_SEMIHOST && + (!semihosting_enabled() || + ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { return false; } switch (cs->exception_index) { + case EXCP_SEMIHOST: + /* This is always a semihosting call; the "is this usermode" + * and "is semihosting enabled" checks have been done at + * translate time. + */ + break; case EXCP_SWI: /* Check for semihosting interrupt. */ if (env->thumb) { |