diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-04-20 17:58:32 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-04-21 18:08:12 +0000 |
| commit | 325b3ceff69c987e90acf9c8ef6f55e646b39767 (patch) | |
| tree | 8787ebd7d09584616ee60180666ef842da515930 /target-arm/helper.c | |
| parent | 581be09434f155ebe0ee7b532c20974843188958 (diff) | |
target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index e495de683b..3247dd31d7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -50,7 +50,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; @@ -59,7 +58,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; @@ -74,7 +72,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). */ - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -83,7 +80,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -92,7 +88,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -100,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -113,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -125,7 +118,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -201,6 +193,8 @@ void cpu_state_reset(CPUARMState *env) cpu_reset_model_id(env, id); env->cp15.c15_config_base_address = tmp; env->cp15.c0_cpuid = cpu->midr; + env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; + #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ |