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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:47 +0000 |
| commit | a984e42c916ad5afdf3f8660f284857547943aa4 (patch) | |
| tree | cd3e835f0f03c47c328bb5a4e03a8b082a9306de /target-arm/helper-a64.h | |
| parent | d6d60581f3f6778de85ee23427006151b5226667 (diff) | |
target-arm: A64: Implement PMULL instruction
Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.
Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper-a64.h')
| -rw-r--r-- | target-arm/helper-a64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index ab9933cab0..43d8bbfc73 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -27,6 +27,8 @@ DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) +DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) |