diff options
| author | Sergey Fedorov <serge.fdrv@gmail.com> | 2015-04-26 16:49:25 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-04-26 16:49:25 +0100 |
| commit | 7ebd5f2e03a00889619bb97e83062d27066d4a26 (patch) | |
| tree | 52580739f4c9e678966c0c96b3b5c68a38a2e57e /target-arm/cpu.h | |
| parent | ef7bab8d73580b48bda83b8d16b5eea8a3ac43fe (diff) | |
target-arm: rename c1_coproc to cpacr_el1
Rename the field holding CPACR_EL1 system register state in AArch64
naming style.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
[PMM: also fixed a couple of missed occurrences in cpu.c]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 083211ce39..d63d9b20f1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -201,7 +201,7 @@ typedef struct CPUARMState { }; uint64_t sctlr_el[4]; }; - uint64_t c1_coproc; /* Coprocessor access register. */ + uint64_t cpacr_el1; /* Architectural feature access control register */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ @@ -1813,7 +1813,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, int fpen; if (arm_feature(env, ARM_FEATURE_V6)) { - fpen = extract32(env->cp15.c1_coproc, 20, 2); + fpen = extract32(env->cp15.cpacr_el1, 20, 2); } else { /* CPACR doesn't exist before v6, so VFP is always accessible */ fpen = 3; |