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authorRichard Henderson <rth@twiddle.net>2011-04-18 15:59:21 -0700
committerRichard Henderson <rth@anchor.twiddle.net>2011-05-31 10:18:06 -0700
commita3b9af162468674cd4bb6e1c7671d7bdabd8699c (patch)
tree965c791219ee9840a05817c3aa18aca9fec890c6 /target-alpha/cpu.h
parent2ace7e55a2b3bdf6a373e5809459a720f71851cf (diff)
target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode.
Reads the page table how PALcode would, except that the virtual page table base register is not used. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha/cpu.h')
-rw-r--r--target-alpha/cpu.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index a1f92abcdc..030ed17679 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -320,6 +320,19 @@ enum {
#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
+/* OSF/1 Page table bits. */
+enum {
+ PTE_VALID = 0x0001,
+ PTE_FOR = 0x0002, /* used for page protection (fault on read) */
+ PTE_FOW = 0x0004, /* used for page protection (fault on write) */
+ PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
+ PTE_ASM = 0x0010,
+ PTE_KRE = 0x0100,
+ PTE_URE = 0x0200,
+ PTE_KWE = 0x1000,
+ PTE_UWE = 0x2000
+};
+
/* Hardware interrupt (entInt) constants. */
enum {
INT_K_IP,