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authorAurelien Jarno <aurelien@aurel32.net>2013-01-01 18:02:23 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-01-31 23:29:36 +0100
commitad153f153da08f5e08bc8e433c0070af53e34e0a (patch)
treeed063d1f4b6903aeb2ac7961392fb3e138626331 /scripts/qapi-visit.py
parentd75c135e6b6255787dfc01ce997862d820ed1d36 (diff)
target-mips: generate a reserved instruction exception on CPU without DSP
On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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