diff options
| author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-06-06 20:43:23 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 18:12:28 +0000 |
| commit | 249ad85a4b4ba6e949bba3c5b9932c389e07249c (patch) | |
| tree | 4cd3dec4dfdc0bb97092812c831150a0180d0a55 /include | |
| parent | 0f4fcf1845fe188901d4ff4cc807bd78690dddd0 (diff) | |
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/loongarch_pch_msi.h | 20 | ||||
| -rw-r--r-- | include/hw/pci-host/ls7a.h | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h new file mode 100644 index 0000000000..f668bfca7a --- /dev/null +++ b/include/hw/intc/loongarch_pch_msi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch 7A1000 I/O interrupt controller definitions + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" +OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) + +/* Msi irq start start from 64 to 255 */ +#define PCH_MSI_IRQ_START 64 +#define PCH_MSI_IRQ_END 255 +#define PCH_MSI_IRQ_NUM 192 + +struct LoongArchPCHMSI { + SysBusDevice parent_obj; + qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM]; + MemoryRegion msi_mmio; +}; diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index bf80e99ce1..089d3e5438 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -15,6 +15,9 @@ #include "qemu/range.h" #include "qom/object.h" +#define LS7A_PCI_MEM_BASE 0x40000000UL +#define LS7A_PCI_MEM_SIZE 0x40000000UL + #define LS7A_PCH_REG_BASE 0x10000000UL #define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) #define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL |