diff options
| author | Efimov Vasily <real@ispras.ru> | 2016-06-22 15:24:54 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-06-29 14:03:46 +0200 |
| commit | f999c0de05103ccd91b3efff282eaa1c0ea93015 (patch) | |
| tree | 211a349b0866d56c77c4802d6e992ed0fc81a7f7 /include | |
| parent | 35a6b23c824e54055f1a2ab30fa5b051a82cdda6 (diff) | |
ICH9 LPC: handle GSI as qdev GPIO
The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are
referenced by pointers. The pointers are initialized at startup by direct access
to the structure fields. This violates Qemu device model.
The patch makes the IRQs handling to use GPIO model.
Signed-off-by: Efimov Vasily <real@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/i386/ich9.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index a09a4459e7..c14490b434 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -68,7 +68,7 @@ typedef struct ICH9LPCState { MemoryRegion rcrb_mem; /* root complex register block */ Notifier machine_ready; - qemu_irq *gsi; + qemu_irq gsi[GSI_NUM_PINS]; } ICH9LPCState; Object *ich9_lpc_find(void); @@ -176,6 +176,8 @@ Object *ich9_lpc_find(void); #define ICH9_LPC_PIC_NUM_PINS 16 #define ICH9_LPC_IOAPIC_NUM_PINS 24 +#define ICH9_GPIO_GSI "gsi" + /* D31:F2 SATA Controller #1 */ #define ICH9_SATA1_DEV 31 #define ICH9_SATA1_FUNC 2 |