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authorBin Meng <bin.meng@windriver.com>2020-09-01 09:39:06 +0800
committerAlistair Francis <alistair.francis@wdc.com>2020-09-09 15:54:18 -0700
commit64ac13633fd416541ea00ff4ae973489bdc33f7a (patch)
tree5976cd70db7d243e661d075ac5923c14a073b0d0 /include
parent7124e27bb8ac16b6aae0e9cd30fb19385430dbb5 (diff)
hw/net: cadence_gem: Add a new 'phy-addr' property
At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
-rw-r--r--include/hw/net/cadence_gem.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 54e646ff79..01c6189a24 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
/* Mask of register bits which are write 1 to clear */
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+ /* PHY address */
+ uint8_t phy_addr;
/* PHY registers backing store */
uint16_t phy_regs[32];