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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-02-05 16:52:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-05 16:52:37 +0000 |
| commit | d3765835ed02f91f0c6cbb452874209a6af4a730 (patch) | |
| tree | 97f83fe7fc2e1732144bab735b1b95a536042694 /include/exec/memattrs.h | |
| parent | 08f1434a71ddf2bdfdb034dcd24b24464d1efd72 (diff) | |
exec: Add target-specific tlb bits to MemTxAttrs
These bits can be used to cache target-specific data in cputlb
read from the page tables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190128223118.5255-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec/memattrs.h')
| -rw-r--r-- | include/exec/memattrs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642098..d4a3477d71 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, |