aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
authorCédric Le Goater <clg@kaod.org>2022-08-17 17:08:27 +0200
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-08-31 14:08:06 -0300
commit2841430e6ae5cee6e58b1f0d86b77c6bbbc8c2d3 (patch)
tree4beff177e37486cc6e84597357a5d32420a2c8b7 /hw
parent72beecc20c72fefb97bc4a4e558ba4e884166629 (diff)
ppc/ppc405: QOM'ify POB
POB is currently modeled as a simple DCR device. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <2bb1a89182523059ecb0e8d20c22a293534dec17.1660746880.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/ppc/ppc405.h12
-rw-r--r--hw/ppc/ppc405_uc.c56
2 files changed, 44 insertions, 24 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d63c2acdc7..4140e811d5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -220,6 +231,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+ Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2c482bc25c..e5604c3421 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
-static uint32_t dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob(void *opaque, int dcrn)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
uint32_t ret;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -266,11 +258,10 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,34 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(dev);
- pob = opaque;
/* No error */
pob->bear = 0x00000000;
pob->besr0 = 0x0000000;
pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405PobState *pob = PPC405_POB(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
+}
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
{
- ppc4xx_pob_t *pob;
+ DeviceClass *dc = DEVICE_CLASS(oc);
- pob = g_new0(ppc4xx_pob_t, 1);
- ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+ dc->realize = ppc405_pob_realize;
+ dc->reset = ppc405_pob_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1373,6 +1372,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+ object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
}
static void ppc405_reset(void *opaque)
@@ -1407,7 +1408,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
- ppc4xx_pob_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
+ return;
+ }
/* OBP arbitrer */
sbd = SYS_BUS_DEVICE(&s->opba);
@@ -1527,6 +1530,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_POB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PobState),
+ .class_init = ppc405_pob_class_init,
+ }, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),