diff options
| author | Vijai Kumar K <vijai@behindbytes.com> | 2021-04-01 23:44:57 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:06 +1000 |
| commit | 8a2aca3d79f8719b9cf79fdcdfbb89bc6bdb522a (patch) | |
| tree | 3d243d29afc90c883c36eaa3810664dfa37c6b22 /hw | |
| parent | 07f334d89d47cba59f8f47fdc8f5983234487801 (diff) | |
hw/riscv: Connect Shakti UART to Shakti platform
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/riscv/shakti_c.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 6e6e63d153..18f70fadaa 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -128,6 +128,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); + /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); @@ -146,6 +153,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); /* * CPU type is fixed and we are not supporting passing from commandline yet. |