diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2011-10-07 09:19:45 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-10-16 11:11:06 +0000 |
| commit | 86fbf97ceb4a9c46a609dd4ae053ba4262b68fe8 (patch) | |
| tree | 38e936612cf6b73d82c406030aeb567c6464dbd4 /hw | |
| parent | 51d9e939b8120d76feb096aeff04368683784541 (diff) | |
i8259: Clear ELCR on reset
The ELCR is actually part of the chipset but we model it here for
simplicity reasons. The PIIX3 clears the ELCR on reset, which was once
broken by 4dbe19e181. Fix this by splitting up pic_init_reset from
pic_reset and clearing the register in the latter.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i8259.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/hw/i8259.c b/hw/i8259.c index 3498c6bf66..d18fc624f0 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -263,10 +263,8 @@ int pic_read_irq(PicState2 *s) return intno; } -static void pic_reset(void *opaque) +static void pic_init_reset(PicState *s) { - PicState *s = opaque; - s->last_irr = 0; s->irr = 0; s->imr = 0; @@ -286,6 +284,14 @@ static void pic_reset(void *opaque) pic_update_irq(s->pics_state); } +static void pic_reset(void *opaque) +{ + PicState *s = opaque; + + pic_init_reset(s); + s->elcr = 0; +} + static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, uint64_t val64, unsigned size) { @@ -297,8 +303,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); if (addr == 0) { if (val & 0x10) { - /* init */ - pic_reset(s); + pic_init_reset(s); s->init_state = 1; s->init4 = val & 1; s->single_mode = val & 2; |