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author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2012-10-15 14:37:04 +1000 |
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committer | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2012-10-29 16:38:26 +1000 |
commit | f12411440b5d9e96af0720dd47b484c1440f4d62 (patch) | |
tree | 0189f8fc433cde6b733bd03897c50cfd9ff835d2 /hw/xilinx_zynq.c | |
parent | 419336a9f934d6a6c7098648bc833137a5db2015 (diff) |
xilinx_spips: Generalised to model QSPI
Extended the xilinx spips controller to model QSPI as well. Paremeterised the
operational difference with the normal spi controller (num_ss_bits, width of the
tx/rx fifo heads etc.). Multiple bus functionality is modelled (needed for QSPI
dual parallel mode. LQSPI is modelled.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'hw/xilinx_zynq.c')
0 files changed, 0 insertions, 0 deletions