diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-02 19:39:11 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-09 21:07:03 +0100 |
| commit | e0bcb9ca36e4f3081c7e6841283646985ed9676b (patch) | |
| tree | 966a3463050e3ea20ff252e85412b3e176bceb80 /hw/sh7750.c | |
| parent | 434254aa5f1a9497710dd10993a72ec434e149a6 (diff) | |
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw/sh7750.c')
| -rw-r--r-- | hw/sh7750.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/hw/sh7750.c b/hw/sh7750.c index 933bbc0c7a..9c39f4b68b 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, portb_changed(s, temp); return; case SH7750_MMUCR_A7: - s->cpu->mmucr = mem_value; - return; + if (mem_value & MMUCR_TI) { + cpu_sh4_invalidate_tlb(s->cpu); + } + s->cpu->mmucr = mem_value & ~MMUCR_TI; + return; case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |