diff options
| author | Anup Patel <anup.patel@wdc.com> | 2020-05-14 15:51:31 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-25 09:11:35 -0700 |
| commit | 3bf03f08999b9a469a61279a04041bcbfadad6a8 (patch) | |
| tree | e43634385ee0e9b1e634c22388d529857daa75d1 /hw/riscv/sifive_u.c | |
| parent | 7774e403f2ac58b3e87bfe8d2f77676501ba893e (diff) | |
hw/riscv: Allow creating multiple instances of CLINT
We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 18301e6fa5..8d2ee9d026 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -703,7 +703,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, - memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, + memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |